BIOS
KP6-LS
Page 4-10
x222: Use of this option may cause conflicts with some system
configurations.
x333: This is used for standard system configurations.
DRAM Data Integrity Mode: Use this option to configure the type of DRAM in
your system.
The default is Non-ECC.
Non-ECC: If your memory is Non-ECC memory, choose this option.
ECC: If your memory is ECC memory, choose this option.
CPU-To-PCI IDE Posting: This option allows the computer to post write cycles
from the CPU to the PCI IDE interface. IDE accesses are posted in the CPU to
PCI buffers, for cycle optimization.
The default is Enabled.
Enabled: Enabled
Disabled: Disabled
System BIOS Cacheable: This allows you to copy your BIOS code from slow
ROM to fast RAM.
The default is Disabled.
Enabled: The option will improve system performance. However, if any
program writes to this memory area, a system error may result.
Disabled: System BIOS non-cacheable.
Video BIOS Cacheable: This option copies the video ROM BIOS to fast RAM
(C0000h to C7FFFh).
The default is Enabled.
Enabled: Enables the Video BIOS Cacheable to speed up the VGA
Performance.
Disabled: Will not use the Video BIOS Cacheable function.
Video RAM Cacheable: This option allows the CPU to cache read/writes of the
video RAM.
The default is Enabled.
Enabled: This option allows for faster video access.
Disabled: Reduced video performance.
Summary of Contents for KP6-LS
Page 2: ...KP6 LS ...
Page 14: ...Introduction KP6 LS Page 1 8 Figure 5 System Block Diagram System Block Diagram ...
Page 17: ...Installation KP6 LS Page 3 1 Section 3 INSTALLATION ...
Page 28: ...Installation KP6 LS Page 3 12 Page Left Blank ...
Page 56: ...BIOS KP6 LS Page 4 28 Page Left Blank ...
Page 58: ...DMI Access KP6 LS Page 5 2 Page Left Blank ...