EPOX EP-D3VA, User Manual, Page: 44 / 90

BIOS Setup
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Chipset Features Setup
Choose the Advanced Chipset Features in the CMOS SETUP UTILITY menu to
display the following menu.
DRAM Timing By SPD : Select Enabled for setting SDRAM timing by SPD.
The Choice: Enabled, Disabled.
DRAM Clock: This setting controls the memory clock. The default is Host Clock.
Host CLK: Sets the memory to run at the same speed of the processors front
side bus. Best used when the processor has a 133MHz bus so the
memory will match it.
HCLK+ 33M: Sets the memory to run at 33MHz faster than the processors front
side bus. Best used when the processor has a 100MHz bus and you
have PC133 SDRAM that you would like to function at 133MHz.
HCLK - 33: Sets the memory to run at 33MHz slower than the processor’s
front side bus. Best used when the processor has a 133MHz bus
and you are limited to using a 100MHz bus for the memory.
SDRAM Cycle Length: This setting defines the CALT (CAS) timing parameter of
the SDRAM in terms of clocks. The default is Auto.
Auto: Best settings are read from SPD EPROM.
2: Provides faster memory performance.
3: Provides better memory compatibility.