EPOX EP-6VBA2, User Manual, Page: 41 / 71

BIOS
EP-6VBA2
Page 4-15
Reset Configuration Data: This setting allows you to clear ESCD data.
The default is Disabled
Disabled: Normal Setting.
Enabled: If you have plugged in some Legacy cards to the system and they were
recorded into ESCD (Extended System Configuration Data), you can
set this field to Enabled in order to clear ESCD.
CPU to PCI Write Buffer: When enabled, up to four D words of data can be
written to the PCI bus without interruting the CPU. When disabled, a write buffer
is not used and the CPU read cycle will not be completed until the PCI bus signals
that it is ready to receive the data.
The Choice: Enabled, Disabled.
PCI Dynamic Bursting: When Enabled, data transfers on the PCI bus, where
possible, make use of the high-performance PCI bust protocol, in which graeater
amounts of data are transferred at a single command.
The Choice: Enabled, Disabled.
PCI Master 0 WS Write: When Enabled, writes to the PCI bus are command
with zero wait states.
The Choice: Enabled, Disabled.
PCI Delay Transaction: The chipset has an embedded 32-bit posted write buffer
to support delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
The Choice: Enabled, Disabled.
PCI #2 Access #1 Retry: This item allows you enabled/disable the PCI #2
Access #1 Retry.
The Choice: Enabled, Disabled.
Slot 1 to Slot 5 Use IRQ No: These settings allow the user to specify what IRQ
will be assigned to PCI devices in the chosen slot. Options available: Auto,3,4,5,
7,9,10,11,12,14 & 15. The defaults are Auto.