EPOX EP-3WXM, User Manual

Page: 36 / 68

BIOS EP-3WXM/2/4
Page 4-10
4-3 Advanced Chipset Features
CMOS Setup Utility – Copyright © 1984 – 1998 Award Software
Advanced Chipset Features
SDRAM CAS Latency Time 3
SDRAM Cycle Time Tras/Trc 6/8
SDRAM RAS-to-CAS Delay 2
SDRAM RAS Precharge Time 2
System BIOS Cacheable Enabled
Video BIOS Cacheable Enabled
Memory Hole At 15M-16M Enabled
Delay Transaction Disabled
On-Chip Video Window Size 64MB
* Onboard Display Cache Setting *
CAS# Latency 3
Paging Mode Control Close
RAS-to-CAS Override by CAS# LT
RAS# Timing Slow
RAS# Precharge Timing Slow
Item Help
___________________________________
Menu Level
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Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the specific features of
the installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communica-
tions between the conventional ISA bus and the PCI bus. It must be stated that these
items should never need to be altered. The default settings have been chosen be-
cause they provide the best operating conditions for your system. The only time you
might consider making any changes would be if you discovered that data was being
lost while using your system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered
if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.