6.1 Peripheral multiplexing description
Following we describe opportunity to use alternative interfaces using the properties of multiplexing pin.
Please refer to the NXP's reference manual and documentation for further details (document name i.MX6UL Reference
Manual).
6.1.1 SPI Interfaces
Using pin multiplexing 's features we may have the following SPI and IIS connections. In the tables below are shown the output signals
on the Connector's module.
ECSPI1 signals interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
63 / 65
CSI_DATA06 / LCD_DATA22
MOSI
+3,3V
73 / 106
CSI_DATA07 / LCD_DATA23
MISO
+3,3V
72 / 108
CSI_DATA04 / LCD_DATA20
SCK
+3,3V
68 / 109
CSI_DATA05 / LCD_DATA21
SS0
+3,3V
153
LCD_DATA05
SS1
+3,3V
152
LCD_DATA06
SS2
+3,3V
151
LCD_DATA07
SS3
+3,3V
Table 26
ECSPI2 signals interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
170 / 111
CSI_DATA02 / UART5_TX_DATA
MOSI
+3,3V
166 / 110
CSI_DATA03 / UART5_RX_DATA
MISO
+3,3V
168 / 23
CSI_DATA00 / UART4_TX_DATA
SCK
+3,3V
171 / 24
CSI_DATA01 / UART4_RX_DATA
SS0
+3,3V
161
LCD_HSYNC
SS1
+3,3V
160
LCD_VSYNC
SS2
+3,3V
62
LCD_RESET
SS3
+3,3V
Table 27
ECSPI3 signals interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
35
NAND_CE1_B / UART2_CTS_B
MOSI
+3,3V
121
UART2_RTS_B
MISO
+3,3V
113
UART2_RX_DATA
SCK
+3,3V
112
UART2_TX_DATA
SS0
+3,3V
Table 28
D N :
4 2
