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EDM 01-17 DAG 7.1S Card User Guide

Chapter 2:
Installation

Introduction

A DAG 7.1S card can be installed in any free PCI-Express slot.

The DAG 7.1S card operates on a single lane PCI-Express, this interface
is capable of providing a maximum throughput of 1.8GB/s for both
receive and transmit.

You can run multiple DAG 7.1S cards on one bus. By default, the DAG
driver supports up to four DAG cards in one system.

DAG Driver
Device

The DAG device driver must be installed before you install the DAG card
itself.

If you have not already completed this please follow the instructions in

EDM04-01 Linux FreeBSD Software Installation Guide

or E

DM 04-02

Windows Software Installation Guide

as appropriate, which are included on

the CD shipped with the DAG card.

Inserting the
DAG Card

To insert the DAG card in the PC follow the steps described below:

•

Turn power to the computer OFF,

•

Remove the PCI bus slot screw and cover,

•

Insert DAG card into PCI-e bus slot ensuring that it is firmly seated in

the slot,

•

Check the free end of the card fits securely into the card-end bracket

that supports the weight of the card,

•

Secure the card with the bus slot screw,

•

Connect the extra power connector located on the top edge of the card.

Note:

Ensure you do this before powering up the computer. Failure

to do so may cause damage to the card.

•

Turn power to the computer ON.

Extra Power
Connector

Version 2: May 2006

Summary of Contents for DAG 7.1S

Page 1: ......

Page 2: ... 7 839 0543 Americas Endace USA Ltd Suite 220 11495 Sunset Hill Road Reston Virginia 20190 United States of America Phone 1 703 382 0155 Fax 1 703 382 0155 Europe Middle East Africa Endace Europe Ltd Sheraton House Castle Park Cambridge CB3 0AX United Kingdom Phone 44 1223 370 176 Fax 44 1223 370 040 Copyright 2006 All rights reserved No part of this publication may be reproduced stored in a retri...

Page 3: ...t that this manual pertains to may include extra components and materials that are not essential to its basic operation but are necessary to ensure compliance to the product standards required by the United States Federal Communications Commission and the European EMC Directive Modification or removal of these components and or materials is liable to cause non compliance to these standards and in ...

Page 4: ......

Page 5: ...on Options 16 Configuration in WYSYCC Style 18 Inspect Interface Statistics 21 Verify Configuration 23 Chapter 4 Capturing Data 25 Starting a Session 25 Setting Captured Packet Length 25 Enabling Disabling Ports 26 High Load Performance 27 Overview 27 Avoiding Packet Loss 27 Detecting Packet Losses 27 Increasing Buffer Size 28 Transmitting 28 Configuring for Transmission 29 Explicit Packet Transmi...

Page 6: ...Guide Chapter 6 Data Formats 39 Overview 39 Generic Header 39 Generic Header cont 40 Type 5 Record 41 Type 7 Record 42 Type 9 Record 42 Type 12 Record 43 Chapter 7 Troubleshooting 45 Reporting Problems 45 Version 2 May 2006 ii 2006 ...

Page 7: ...traffic with precision timestamping capability on 4 x STM 1 or 2 x STM 2 interfaces Purpose of this User Guide Description The purpose of this User Guide is to provide you with an understanding of the DAG card architecture and functionality and to guide you through the following Installing the card and associated software and firmware Configuring the card for your specific network requirements Run...

Page 8: ...as an operating system installed However for convenience a copy of Debian Linux 3 1 Sarge is provided as a bootable ISO image on the CDs that is shipped with the DAG card To install either the Linux FreeBSD or Windows operating system please refer to the following documents which are also included on the CD that is shipped with the DAG card EDM04 01 Linux FreeBSD Software Installation Guide EDM 04...

Page 9: ...taneously The key features of the card are Four interfaces allow full line rate capture and processing for 4 x STM 1 OC 3 or 2 x STM 2 OC 12 Fully programmable Intel IXP Network Processor PCI Express bus interface 1244Mpps raw transmit and receive bandwidth Combined FPGA and network processor architecture Channelised and concatenated support ATM AAL2 and AAL5 segmentation and reassembly PoS IP fil...

Page 10: ...high resolution per packet timestamps which can be accurately synchronised Time stamped packet records are then stored in the lower FIFO Note For further information on the DUCK and time synchronising please refer to Chapter 8 Synchronising Clock Time later in this User Guide An Intel IXP network processor is logically located next to the main FPGA The main FPGA can route packets to either the IXP...

Page 11: ...Pv4 and IPv6 and or UDP TCP SCTP port number Up to 1024 IP header classification rules Up 254 UDP TCP SCTP port or ICMP type rules can set per IP header classification Classification rules are assigned a user defined 14 bit identifier Packets matching classification rules are assigned the matching rule s identifier Programmable actions may be associated with each rule identifier For example the pa...

Page 12: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 6 2006 ...

Page 13: ...FreeBSD Software Installation Guide or EDM 04 02 Windows Software Installation Guide as appropriate which are included on the CD shipped with the DAG card Inserting the DAG Card To insert the DAG card in the PC follow the steps described below Turn power to the computer OFF Remove the PCI bus slot screw and cover Insert DAG card into PCI e bus slot ensuring that it is firmly seated in the slot Che...

Page 14: ... card uses industry standard Small Form factor Pluggable SFP optical transceivers The transceivers consists of two parts Mechanical chassis attached to the circuit board Transceiver unit which may be inserted into the chassis Note You must select the correct transceiver type to match the optical parameters of the network to which you want t connect Configuring the card with the wrong transceiver t...

Page 15: ...s above the upper limit the optical receiver saturates and fails to function When power is below the lower limit the bit error rate increases until the device is unable to obtain lock and fails In extreme cases excess power can damage the receiver When you set up the DAG card measure the optical power at the receiver and ensure that it is well within the specified power range To adjust the input p...

Page 16: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 10 2006 ...

Page 17: ... characteristics Sample dagthree and dagchan outputs are shown later in this chapter LEDs and Inputs Before you begin to configure the DAG card it is important to understand the function of the various LEDs associated with the card as well as the sockets on the PCI bracket RJ45 socket for time Synchronisation Input SFP Optics PHY Main FPGA IXP Network Processor Pwr PHY SODIMM Expandable Memory 3 4...

Page 18: ...s unchannelized POS ATM OC 3c OC 12c STM 1c and STM 4c standards for transmit and receive Additionally channelized ATM HDLC receive is supported on a single port only Because of its flexibility the correct link layer configuration needs to be supplied to the card for it to function as expected A successful DAG card capture session is accomplished by checking the receiver ports optical signal level...

Page 19: ...linx dag71spci conc terf bit Load Latest Available PHY FPGA Images dag endace dagld x d dag0 xilinx dag71pp erf bit xilinx dag71spp conc terf bit Concatenated Configuration cont The table below shows the available configurations Note Not all configurations are available within a single FPGA image Image Number of Ports Port Type VC Type and Number Demapper 1 4 STM 1c 4 x VC 4 4 x VC 4 4c PoS ATM AT...

Page 20: ...3 vc3 scramble tu11 async SONET B oc3 vc3 scramble tu11 async SONET C oc3 vc3 scramble tu11 async SONET D oc3 vc3 scramble tu11 async E1 T1 status E1 T1 A no_payload notxais E1 T1 B no_payload notxais E1 T1 C no_payload notxais E1 T1 D no_payload notxais Concatenated Configuration cont Display Card Configuration cont Phy status AMCC1213 eql fcl noreset Concatenated Demapper Status pscramble crc32 ...

Page 21: ...ters involved to set the framing are The link speed oc3 oc12 The clock master master slave The payload mapping itself vc4c vc4 vc3 Sometimes the framer mapper requires a reset in order to synchronize after a configuration change In that case the argument reset should be used in dagconfig When a channelized framing is chosen a channelized firmware is needed When a concatenated or clear framing is c...

Page 22: ...Generate SONET tx clock internally slave Drive SONET tx clock from rx clock no pscramble un set Payload Scramble nocrc No PoS CRC checking crc16 PoS CRC16 checks enabled crc32 PoS CRC32 checks enabled no aidle When set pass through received idle cells slen Sets number of bytes of packet payload captured Defaults to 48 for PoS fixed at 52 for ATM no varlen Dis enable variable length capture Otherwi...

Page 23: ...re memory allocated to streams 0 1 rxonly Assign all buffer memory to receive streams txonly Assign all buffer memory to transmit streams rxtx Assign buffer memory to transmit and receive streams coreon TBD coreoff TBD e1_crc TBD e1_unframed TBD t1 TBD t1_esf TBD t1_sf TBD t1_unframed TBD 2006 17 Version 2 May 2006 ...

Page 24: ...A nolaser detect nosignal nosfppwr SFP B nolaser detect nosignal nosfppwr SFP C nolaser detect nosignal nosfppwr SFP D nolaser detect signal sfppwr Port status Port A nolock oc12 core_on nofifo_error slave Port B nolock oc12 core_on nofifo_error slave Port C nolock oc12 core_on nofifo_error slave Port D lock oc12 core_on nofifo_error slave SONET SDH status SONET A oc12 vc4c scramble tu11 async SON...

Page 25: ...P D nolaser detect signal sfppwr Port status Port A nolock oc12 core_on nofifo_error slave Port B nolock oc12 core_on nofifo_error slave Port C lock oc12 core_on nofifo_error slave Port D lock oc12 core_on nofifo_error slave SONET SDH status SONET A oc12 vc4c scramble tu11 async SONET B oc12 vc4c scramble tu11 async SONET C oc12 vc4c scramble tu11 async SONET D oc12 vc4c scramble tu11 async E1 T1 ...

Page 26: ...M 01 17 DAG 7 1S Card User Guide pscramble crc32 pos pscramble crc32 pos GPP varlen slen 48 align64 PCI Burst Manager 33Mhz buffer size 256 rx_streams 1 tx_streams 1 mem 240 16 Version 2 May 2006 20 2006 ...

Page 27: ...dicates a signal problem related to either low light levels reaching the optical receivers or true SONET level errors as reported by SONET equipment operating the link to be monitored lop Loss of pointer If set the pointer processing logic has not locked to the SONET frame It may indicate incorrect OC 3 vs OC 12 setting oof Out of frame If set the section overhead processor is not locked to the SO...

Page 28: ...C 1 0 1 1 1 1 1 0xfd00 lop D 1 0 1 1 1 1 1 0x0100 lop Port LOS LOF OOF B1 B2 B3 REI C2 PTR C 1 0 1 1 1 1 1 0xe200 Lop D 1 0 1 1 1 1 1 0x5300 Lop ATM Cell Stream Example An example for an ATM cell stream at OC 12 is ports A and B are unused Port LOS LOF OOF B1 B2 B3 REI C2 PTR A 1 1 1 0 0 0 0 0xe800 lop B 1 1 1 0 0 0 0 0xe800 lop C 0 0 0 0 0 0 0 0x1300 valid D 0 0 0 0 0 0 0 0x1300 valid No error bi...

Page 29: ...ion is verified as being correct by checking settings and path label for any errors as described in the following steps Ensure los first column is zero and check light levels Ensure oof and lof are zero otherwise change OC 3 settings to OC 12 or vice versa Ensure no bit interleaved parity errors occur otherwise check cabling and light levels Ensure path label C2 is correct as per the payload Ensur...

Page 30: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 24 2006 ...

Page 31: ...pture session although you may want to omit it for automated trace runs By default dagsnap will run indefinitely but can be stopped using CTRL C You can also configure dagsnap to run for a fixed time period then exit Setting Captured Packet Length Snaplength You can use dagconfig to set the length of the packets you want to capture By default the snaplength slen which is the portion of the packet ...

Page 32: ...below shows configuration for variable length full packet capture dagconfig d dag0 varlen slen 2040 In fixed length novarlen mode any packets that are longer than the slen value are truncated to that length in the same way as for varlen capture However any packets that are shorter than the slen value will produce records that are padded out to the slen length The example below shows configuration ...

Page 33: ...lls the following message displays on the PC screen kernel dagN pbm safety net reached 0xNNNNNNNN The same message is also printed to log var log messages In addition when the PC buffer fills the Data Capture LED on the card will flash or flicker or may go OFF completely In Windows no screen message displays to indicate when the buffer is full Please contact Endace Customer Support at support enda...

Page 34: ...dows the upper limit is 32MB This is usually sufficient however if you do need to increase the amount of reserved memory please contact Endace customer support at support endace com for more information The dsize option sets the amount of memory used per DAG card in the system Note The value of dsize multiplied by the number of DAG cards in the system must be less than the amount of physical memor...

Page 35: ...RP ping or router discovery protocols It will only transmit packets explicitly provided by the user This capability allows you to use the DAG card as a simple traffic load generator It can also be used to retransmit previously recorded packet traces The packet trace is transmitted at 100 line rate The packet timing of the original trace file is not reproduced Dagflood Tool The dagflood tool can tr...

Page 36: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 30 2006 ...

Page 37: ...nated universal time UTC You can obtain an accurate time reference by connecting an external clock to the DAG card using the time synchronisation connector Alternatively you can use the host PCs clock in software as a reference source without any additional hardware Each DAG card can also output a clock signal for use by other cards Common Synchronization The DAG card time synchronisation connecto...

Page 38: ...ution of 2 32 seconds or approximately 233 picoseconds The ERF timestamp allows you to find the difference between two timestamps using a single 64 bit subtraction You do not need to check for overflows between the two halves of the structure as you would need to do when comparing Unix time structures Different DAG cards have different actual resolutions This is accommodated by the lowermost bits ...

Page 39: ... timeout in seconds default 60 l threshold health threshold in ns default 596 Option default RS422 in none out none None in none out rs422in RS422 input hostin Host input unused overin Internal input synchronise to host clock auxin Aux input unused rs422out Output the rs422 input signal loop Output the selected input hostout Output from host unused overout Internal output master card Set DAG clock...

Page 40: ...r Freq 30ppb Phase 15ns Worst Freq 2092838ppb Worst Phase 33473626ns crystal Actual 100000023Hz Synthesized 67108864Hz input Total 225 Bad 0 Singles Missed 1 Longest Sequence Missed 1 start Thu Apr 28 14 55 20 2005 host Thu Apr 28 14 59 06 2005 dag Thu Apr 28 14 59 06 2005 Connecting the Time Distribution Server You can connect the TDS 2 module to the DAG card using standard RJ 45 Ethernet cable i...

Page 41: ...d 11921ns Failures 0 Resyncs 0 error Freq 1836ppb Phase 605ns Worst Freq 143377ppb Worst Phase 88424ns crystal Actual 49999347Hz Synthesized 16777216Hz input Total 87039 Bad 0 Singles Missed 0 Longest Sequence Missed 0 start Wed Apr 27 14 27 41 2005 host Thu Apr 28 14 38 20 2005 dag Thu Apr 28 14 38 20 2005 Two Cards No Reference Overview If you are using two DAG cards in a single host PC with no ...

Page 42: ...g No active input Free running Note The slave card configuration is not shown as the default configuration will work Synchronising with Host To prevent the DAG card clock time stamps drifting against UTC the master can be synchronised to the host PC s clock which in turn utilises NTP This then provides a master signal to the slave card Configure one card to synchronize to the PC clock and output a...

Page 43: ... 5 In B 6 In A 8 1 8 1 Top Front 8 1 RJ45 Socket 7 Out B 8 Out B Normally you should connect the GPS input to the A channel input pins 3 and 6 The DAG card can also output a synchronization pulse for use when synchronizing two DAG cards without a GPS input The synchronization pulse is output on the Out A channel pins 1 and 2 Ethernet Crossover Table You can use a standard Ethernet crossover cable ...

Page 44: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 38 2006 ...

Page 45: ...ti Channel AAL2 Frame Record 12 TYPE_AAL2 Reassembled AAL2 Frame 18 The ERF file contains a series of ERF records with each record describing one packet An ERF file consists only of ERF records there is no special file header which allows concatenation and splitting to be performed arbitrarily on ERF record boundaries Generic Header All ERF records share some common fields Timestamps are in little...

Page 46: ... 0 Enumerates capture interface 0 3 2 Varying record lengths 3 Truncated record insufficient buffer space 4 RX error link layer error 5 DS error internal error 6 Reserved 7 General direction bit This bit has two uses it indicates from where a packet has arrived either the host or line and enables the XScale to target the packet at either the host or line The direction bit can be interpreted in the...

Page 47: ...rpretation of this quantity depends on physical medium Type 5 Record The format of the multichannel header for channelised links used for TYPE_MC_HDLC is shown below This header is divided into several bit fields as follows 0 9 Connection number 0 511 10 15 Reserved 16 23 Reserved 24 FCS Error 25 Short Record Error 5 Bytes 26 Long Record Error 2047 Bytes 27 Aborted Frame Error 28 Octet Error 29 Lo...

Page 48: ...OAM Cell CRC 10 Error not implemented 27 OAM Cell 28 1st Rec This is the first record received since the connection was configured 29 31 Reserved Type 9 Record The format of the multichannel header for channelized links used for TYPE_MC_AAL5 is shown below This header is divided into several bit fields as follows 0 9 Connection number 0 1023 10 15 Reserved 16 19 Physical port 0 15 cell was capture...

Page 49: ...ided into several bit fields as follows 0 9 Connection number 0 1023 10 12 Reserved possible extra connection numbers 13 15 Reserved indication of AAL2 type 16 19 Physical port 0 15 cell was captured on 20 Reserved 21 1st Rec This is the first record received since the connection was configured 22 MAAL Error 23 Length Error 24 31 Reserved 2006 43 Version 2 May 2006 ...

Page 50: ...EDM 01 17 DAG 7 1S Card User Guide Version 2 May 2006 44 2006 ...

Page 51: ...onfiguration Host PC operating system version DAG software version package in use Any compiler errors or warnings when building DAG driver or tools For Linux and FreeBSD messages generated when DAG device driver is loaded These can be collected from command dmesg or from log file var log syslog Output of daginf Firmware versions from dagrom x Physical layer status reported by dagthree Network link...

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