Endace DAG 7.1S, User Manual

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EDM 01-17 DAG 7.1S Card User Guide
Card
Architecture
Serial SONET/SDH optical data is received by four optical interfaces, and
passed through deserializers.
The network data feeds immediately into two physical layer FPGAs. The
SONET/SDH payload data is then sent to the main FPGA.
The FPGA contains the packet record processor, PCI Express interface
logic and the DAG Universal Clock Kit (DUCK) timestamp engine. The
DUCK provides high resolution per packet timestamps which can be
accurately synchronised. Time stamped packet records are then stored in
the lower FIFO.
Note: For further information on the DUCK and time synchronising
please refer to Chapter 8 : Synchronising Clock Time later in this
User Guide.
An Intel IXP network processor is logically located next to the main
FPGA. The main FPGA can route packets to either the IXP network
processor for additional processing before routing onto the host or directly
to the host via the PCI-Express port.
The following diagram shows the card’s major components and the flow
of data.
Version 2: May 2006 4 ©2006