Endace DAG 6.1S User Manual Download

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Summary of Contents for DAG 6.1S

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Page 2: ...839 0543 support endace com www endace com Endace USA Ltd Suite 220 11495 Sunset Hill Road Reston Virginia 20190 United States of America Phone 1 703 382 0155 Fax 1 703 382 0155 support endace com ww...

Page 3: ...eral Communications Commission FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipme...

Page 4: ...Interpreting DAG 6 1S Card LED Status 9 4 2 DAG 6 1S Card LED Display Functions 10 4 3 Configuration in WYSYCC Style 11 4 4 dagsix Utility 14 4 5 DAG 6 1S Card Capture Session 14 4 6 Inspect PoS Inter...

Page 5: ...EDM 01 11v8 DAG 6 1S Card User Guide 2005 ii Version 8 May 2006...

Page 6: ...anual is available on the installation CD In this chapter This chapter covers the following sections of information User Manual Purpose DAG 6 1S Card Product Description DAG 6 1S Card Architecture DAG...

Page 7: ...S PCI X Card Installed in a PCI X 1 0 slot the DAG 6 1S card only operates at 66 100 and 133 MHz PCI X for full packet capture at line rate and allows recording of all header information and or payloa...

Page 8: ...the DAG 6 1S card major components and data flow Figure 1 2 DAG 6 1S Card Major Components and Data Flow 1 4 DAG 6 1S Card Extended Functions Description The shipped version of the DAG 6 1S does not c...

Page 9: ...Debian 3 1 Sarge Linux system is included on the Endace Software Install CD Endace currently supports Windows XP Windows Server 2000 Windows Server 2003 FreeBSD RHEL 3 0 and Debian Linux operating sys...

Page 10: ...This chapter covers the following sections of information Installation of Operating System and Endace Software Insert DAG 6 1S Card into PC Installation of Operating System and Endace Software 2 1 In...

Page 11: ...that supports the card weight Step 3 Replace bus Slot Screw Secure card with screw Step 4 Power up computer 2 3 Connect Card Ports Description There is one square plastic SC type optical connector on...

Page 12: ...tion Part No Fibre Data Rate Max Power dBm Min Power dBm Nominal Pwr dBm GT10 RXU SMF 10Gbps 0 17 9 In this chapter This chapter covers the following sections of information Interpreting DAG 6 1S Card...

Page 13: ...Description Splitters have the insertion losses marked on packaging or in accompanying documentation A 50 50 splitter will have an insertion loss of between 3 dB and 4 dB on each output 90 10 splitter...

Page 14: ...on in this section regarding reporting of problems In this chapter This chapter covers the following sections of information Interpreting DAG 6 1S Card LED Status DAG 6 1S Card LED Display Functions C...

Page 15: ...9 PPS Out Pulse Per Second Out indicates card is sending a clock synchronization signal LED 10 PPS In Pulse Per Second In indicates card is receiving an external clock synchronization signal The LED s...

Page 16: ...f phy no fcl un set facility loopback on downstream side of phy no eql un set equipment loopback on downstream side of phy no pscramble un set Packet over SONET scrambling no crc Dis enable PoS CRC32...

Page 17: ...PoS nopscramble nocrc nocrcstrip nopmin nopmax long 1502 short 9 packet varlen slen 48 align64 packetA drop 0 pcix 66MHz 64 bit buf 32MB rxstreams 1 txstreams 0 mem 0 0 Step 2 Configure DAG 6 2S Card...

Page 18: ...mode no lsfcl un set facility loopback on line side of phy no lseql un set equipment loopback on downstream side of phy no fcl un set facility loopback on downstream side of phy no eql un equipment l...

Page 19: ...l Signal Levels The DAG 6 1S card supports 1310 nanometer singlemode fibre attachments with optical signal strength between 0 dBm and 17 dBm If there is doubt check card receiver ports light levels ar...

Page 20: ...RAI Receive Alarm Indication The optics report a receive error One or more of the following two bits will also be set RLE Receive Lock Error The optics report a failure in clock recovery from the rece...

Page 21: ...ndace dagsix d dag0 ei RAI RLE RPA LOS LOC OOF LOF LOP FCS_ERR GOOD_PACKET RXF BIPI BIP2 BIP3 C2 RX_PARITY TEMP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 44 0 0 0 0 0 0 0 0...

Page 22: ...this case RPA the Framing LOF OOF and Pointer LOP errors can still be used to detect an error condition Correct configuration In order to correct the configuration proceed as follows Ensure RAI RLE an...

Page 23: ...s report a failure in clock recovery from the received signal RPA Receive Power Alarm The optics report insufficient optical input power 30dBm LOS Loss Of Signal The framer reports there is either no...

Page 24: ...framer is not locked to the SONET stream LOF Loss Of Frame The framer has asserted OOF for more than 3 milliseconds LOP Loss Of Pointer The framer cannot find the SONET SDH frame pointers LOF Loss Of...

Page 25: ...0 0 0 0 0 0 0 0 0 0 5458160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE The first second has high values as the counters have accumulated th...

Page 26: ...re as follows 16 PoS CF Cisco HDLC RX_PARITY Receive parity error count between the framer and receive FPGA TEMP Temperature of Rx FPGA in degrees Celsius Optical light levels in LAN mode The followin...

Page 27: ...levels Ensure no bip errors occur otherwise check cabling and light levels Ensure the scrambling and CRC settings are ok Little or no data information On WAN links it can happen that there is very lit...

Page 28: ...type and configuration 3 Host PC operating system version 4 DAG software version package in use 5 Any compiler errors or warnings when building DAG driver or tools 6 For Linux and FreeBSD messages ge...

Page 29: ...Starting the capture of data involves a typical measurement session the card operating in variable length mode starting and stopping the session Process The following process describes starting a data...

Page 30: ...gsix d dag0 slen 1552 Values of slen higher than the default may lead to increased packet loss during captures under high link load due to limited PCI X bandwidth Starting a capture session A capture...

Page 31: ...ecessary to use a faster disk or disk array If records are being processed in real time a faster host CPU may be required Increasing buffer size The host PC buffer can be increased to deal with bursts...

Page 32: ...EDM 01 11v8 DAG 6 1S Card User Guide 2005 27 Version 8 May 2006...

Page 33: ...TC Accurate time reference can be obtained from an external clock by connecting to the DAG card using the synchronization connector or the host PCs clock can be used in software as a reference source...

Page 34: ...shold health threshold in ns default 596 Option default RS422 in none out none None in none out rs422in RS422 input hostin Host input unused overin Internal input synchronize to host clock auxin Aux i...

Page 35: ...lock If a PC is running NTP to synchronize its own clock then the DUCK clock is less smooth because the PC clock is adjusted in small jumps However overall the DUCK clock does not drift away from UTC...

Page 36: ...orrect then one card is configured as the clock master for the other Locking cards together Although the master card s clock will drift against UTC the cards are locked together The cards are locked t...

Page 37: ...377ppb Worst Phase 88424ns crystal Actual 49999354Hz Synthesized 16777216Hz input Total 87464 Bad 0 Singles Missed 0 Longest Sequence Missed 0 start Wed Apr 27 14 27 41 2005 host Thu Apr 28 14 59 14 2...

Page 38: ...0 Singles Missed 1 Longest Sequence Missed 1 start Thu Apr 28 14 55 20 2005 host Thu Apr 28 14 59 06 2005 dag Thu Apr 28 14 59 06 2005 Connecting time distribution server The TDS 2 module connects to...

Page 39: ...socket connector pin outs Figure 6 1 RJ45 Plug and Socket Connector Pin outs Out pin connections Normally the GPS input should be connected to the A channel input pins 3 and 6 The DAG card can also o...

Page 40: ...EDM 01 11v8 DAG 6 1S Card User Guide 2005 35 Version 8 May 2006...

Page 41: ...applied Table Table 7 1 shows the generic variable length record The diagram is not to scale timestamp timestamp type flags rlen lctr wlen rlen 16 bytes of record Table 7 1 Generic Variable Length Rec...

Page 42: ...PCI bus to storage Lctr loss counter A 16 bit counter recording the number of packets lost since the previous record Records can be lost between the DAG card and memory hole due to overloading on PCI...

Page 43: ...n the first of January 1970 The high 32 bits contain the integer number of seconds while the lower 32 bits contain the binary fraction of the second This allows an ultimate resolution of 2 32 seconds...

Page 44: ...example code showing how a 64 bit ERF timestamp erfts can be converted into a struct timeval representation tv unsigned long long lts struct timeval tv lts erfts tv tv_sec lts 32 lts lts 0xffffffffULL...

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