Endace DAG 4.5G2 Card, User Manual

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EDM 01-17 DAG 4.5G2/G4/GF Card User Guide
The DAG 4.5G2 card is shown below:
SFP Cages
FPGA with
Heatsink fitted
9-pin socket for time
synchronization
Pluggable Optical
Connectors x 2.
Note: Pluggable
copper connectors
are also supported.
Note : The DAG 4.5G2/GF card is capable of simultaneous capture and
transmission at full line rate across both ports.
Card
Architecture Serial Ethernet network data received by two 1000Base interfaces flows
directly into the Field Programmable Gate Array (FPGA).
The FPGA contains the packet processor, PCI-X interface logic and the
DAG Universal Clock Kit (DUCK) timestamp engine. The DUCK
provides high resolution per-packet timestamps which can be accurately
synchronized.
Note: For further information on the DUCK and time synchronizing
please refer to Chapter 5: Synchronizing Clock Time later in this
User Guide.
Because of component close association, packets are time-stamped
accurately. Time stamped packet records are stored in an external FIFO
memory before transmission to the host.
©2005-2006 4 Version 4: August 2006