Figure 17: MIPI CSI Interface with Zynq-7000/7-Series Modules
Tables 30 and 31 describe the hardware changes required to operate the MIPI CSI interfaces in combination
with older FPGA families. By default module connector pins: C-160/162, C-145/147 and C-154/156 are used
for MIPI 0, while pins C-161/163, C-164/166 and C-157/159 are used for MIPI 1.
The clock pairs on module connector pins C-151/153 and C-148/150 respectively are only used for older FPGA
families, such as Zynq-7000 series.
FPGA Family
Remove
Equip
Zynq Ult
-
-
Zynq-7000 (and similar Intel FPGA families)
R1005 - R1006
R1007 - R1013
Table 30: MIPI Connector 0 CSI - Hardware Changes for older FPGA Families
FPGA Family
Remove
Equip
Zynq Ult
-
-
Zynq-7000 (and similar Intel FPGA families)
R1019 - R1020
R1021 - R1027
Table 31: MIPI Connector 1 CSI - Hardware Changes for older FPGA Families
6.10
Clock Architecture
The ST1 base board provides the user with a diversity of clock configuration options. The board
is equipped with a clock generator programmable via I2C having as reference a 100 MHz clock from an
oscillator (Y801). Alternatively, a user oscillator (Y800) with another frequency can be used as reference -
this part is not equipped by default on the board.
The ST1 base board may be optionally equipped with a voltage-controlled oscillator (Y802) - this
part is not equipped by default.
Figure 18 describes the clocking architecture available on the board. For further information please refer to
the ST1 Base Board User Schematics [4].
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Version 02, 23.07.2020
