FPGA_INIT# signal is also connected to a regular FPGA pin (FPGA_INIT#_R, package pin AD9) via a 47 k
Ω
resistor and can be used to reset the FPGA logic. In this case, internal pull-up must not be used for this
signal, in order to be able to reset the logic via FPGA_INIT# pin available on the module connector.
2.14
LEDs
Four LEDs are available on the KX2 FPGA module and they are connected to the FPGA logic.
Table 19 shows the pin locations of the FPGA LEDs.
Signal Name
FPGA Pin
Remarks
LED0#
U9
User function/active-low
LED1#
V12
User function/active-low
LED2#
V13
User function/active-low
LED3#
W13
User function/active-low
Table 19: LEDs
2.15
DDR3 SDRAM
The DDR3 SDRAM on the KX2 FPGA module is operated at 1.35 V (low power mode) or at 1.5 V,
depending on a selection signal. Four 16-bit memory chips are used to build a 64-bit wide memory.
Note that for FPGAs in FFG packages the memory interface supports speeds of up to 1600 Mb/s, while for
devices in the FBG packages it supports up to 800 Mb/s.
The maximum memory bandwidth on the KX2 FPGA module is:
•
FFG package devices
: 1600 Mbit/sec
×
64 bits = 12800 MB/sec
•
FBG package devices
: 800 Mbit/sec
×
64 bits = 6400 MB/sec
Note that for DDR3 low power mode (DDR3L) the speed can be lower than mentioned above. For details,
refer to the Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics [18].
2.15.1
DDR3 SDRAM Type
Table 20 describes the memory availability and configuration on the KX2 FPGA module.
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Version 06, 25.07.2019
