23/04/2019
32 / 43
Version 1.09
3.0 controller includes a 32 Bit ARM926 core operating at 200 MHz using a 19.2 MHz crystal oscillator.
It can access the I
2
C bus, SPI flash of the FPGA and exchange debug or control information with the
USB 2.0 UART controller over UART. A JTAG interface is available on connector J801 to debug and
download the application.
By default, the PMODE pins of the FX3 are configured for SPI boot with USB fall back (refer to Table
25). Hence, the application code can be stored in a dedicated 16 Mbit SPI flash that is read during
startup. If no valid boot image is found, the FX3 tries to load the application from USB. By removing
R301 and assembling 10 k to R300, the boot mode can be set to USB boot only.
To temporarily prevent the FX3 to boot from the SPI flash R326 can be short circuited. The location of
R326 is shown in Figure 8.
PMODE[2:0]
Boot from
Comments
F00
Sync ADMUX (16 Bit)
Not selectable
F01
Async ADMUX (16 Bit)
Not selectable
F11
USB boot
Remove R301 and assemble 10 k to
R300
F0F
Async RAM (16 Bit)
Not selectable
F1F
I
2
C, on failure USB boot is enabled
Not selectable
1FF
I
2
C only
Not selectable
0F1
SPI, on failure USB boot is enabled
Default
Table 25: Boot mode settings
Figure 8: Location of R326