23/04/2019
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Version 1.09
Comment
Signal
Connector Pin
Signal
Comment
VCC_IO
1
2
VCC_IO
SRST#_RDY#
3
4
GND
FPGA_TDI
5
6
GND
FPGA_TMS
7
8
GND
FPGA_TCK
9
10
GND
GND
11
12
GND
FPGA_TDO
13
14
GND
Not Connected
15
16
GND
SVD_P168
17
18
GND
SVD_P170
19
20
GND
Table 6: J800
–
FPGA JTAG connector
2.8.7
J801
–
FX3 Connector
The main purpose of this connector is to access the JTAG port of the Cypress FX3 USB 3.0 controller. In
addition, this connector feeds out four GPIO pins of the FX3 that can be used if the slave FIFO interface
is not operated in 32 Bit mode. The SYSMON and VBAT signals are also accessible on this connector as
well as the FX3 reset signal that can be pulled down to reset the Cypress FX3 USB controller. All signals
on this connector are ESD protected.
Comment
Signal
Connector Pin
Signal
Comment
12V
VCC_MAIN
1
2
FX3_RESET_EXT#
GND
3
4
VCC_5V
VCC_3V3
5
6
BOOT_MODE
VBAT_IN
7
8
GND
SYSMON_GPI
9
10
SYSMON_GPO#
FX3_TRST#
11
12
FX3_GPIO0
FX3_TMS
13
14
FX3_GPIO1
FX3_TDO
15
16
FX3_GPIO2
FX3_TDI
17
18
FX3_GPIO3
FX3_TCK
19
20
GND
Table 7: J801
–
FX3 connector
Warning
The IO pins are directly connected to the Cypress FX3 USB 3.0 controller or other
peripherals. Only apply VCC_IO compliant voltages to the IO pins. Any other voltages
may damage the FX3 as well as other devices on the Mars PM3 Board.