Echelon 14315R, User Manual

Page: 70 / 99

60 LonWorks Router Design Issues
PCB Layout Guidelines
Printed circuit board (PCB) layout for a Router 5000 is similar to layout for a
Neuron 5000 Processor, and should include the following general features:
• Star-Ground Configuration: Arrange the various blocks of the device that
directly interface with off-board connections (the network, any external
I/O, and the power supply cable) so that they are together along one edge
of the PCB.
•
ESD Keepout Area: Consider the area around the network connection
traces and components as “ESD Hot”. The PCB layout should be
designed so that substantial ESD hits from the network discharge
directly to the star-ground center point.
•
Clamp Diodes: For transceivers that use differential receive signals (such
as the TP/XF-1250 transceiver) use four diodes to clamp the transceiver’s
differential receive signals to ground during ESD and surge transients.
• Ground Return for a Router 5000: A Router 5000 has internal protection
circuitry built into its CP[4..0] pins. When an ESD or surge transient
comes in from the network, the portion of the transient that makes it to
the Router 5000 is clamped to the chip’s V
DD33
power pins and ground
pins. Be sure to provide a short and wide ground path from the Router
5000 back to the center of the star ground.
•
Ground Planes: As ground is routed from the center of the star out to the
function blocks on the board; planes or very wide traces should be used to
lower the inductance (and therefore the impedance) of the ground
distribution system.
• V
DD33
Decoupling Capacitors: A good rule of thumb is to provide at least
one V
DD33
decoupling capacitor to ground for each V
DD33
power pin on an
IC in the design. For SMT devices like a Router 5000, each decoupling
capacitor should be placed on the top layer with the chip, and placed as
close as possible to the chip to minimize the length of V
DD33
trace between
the capacitor and the chip’s V
DD33
pad.
Figure 30 on page 61 shows a portion of the top layer of a 4-layer PCB layout for
the Router 5000 half-router for a TP/XF-1250 transceiver, including the
differential driver circuit, and the comparator circuit, and the other building
blocks of a PCB design. The figure shows a rectangle for the placement of the
TPT/XF-1250 transceiver PCB, which is mounted above the main board.
See the
Connecting a Neuron 5000 Processor to an External Transceiver
Engineering Bulletin for more information about connecting external
transceivers to Neuron 5000 Processors, including the Router 5000. See
Chapters 3 and 4 of the Series 5000 Chip Data Book for additional information
about PCB layout and electromagnetic compatibility (EMC) design guidelines for
a Series 5000 Chip, including the Router 5000.