e2v CCD42-90, Manual

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© e2v technologies (uk) limited 2014
Document subject to disclaimer on page 1 A1A-100026 Version 9, page 7
ELECTRICAL INTERFACE
CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
PGA PIN REF DESCRIPTION
CLOCK AMPLITUDE OR DC LEVEL (V)
(see Note 8)
MAX RATINGS
with respect to
V
SS
(V)
Min Typical Max
A1, A8, C1,
C8, F2, F7
SS Substrate See Note 9
-
D8
I
Ø1
Image clock phase 1 8 10 15 ±20
E8
I
Ø2
Image clock phase 2 8 10 15 ±20
F8
I
Ø3
Image clock phase 3 8 10 15 ±20
D4 RØ1 (L) Register clock phase 1L 8 11 15 ±20
E4 RØ2 (L) Register clock phase 2L 8 11 15 ±20
D5 RØ1 (R) Register clock phase 1R 8 11 15 ±20
E5 RØ2 (R) Register clock phase 2R 8 11 15 ±20
F6 RØ3 Register clock phase 3 8 11 15 ±20
E3 ØR (L) Reset gate L 9 12 15 ±20
E6 ØR (R) Reset gate R 9 12 15 ±20
E2 ØSW (L) Summing well gate L 9 11 15 ±20
E7 ØSW (R) Summing well gate R 9 11 15 ±20
F3 DG Dump gate (see Note 10) -0.5 0 15 ±20
D3 OG1 (L) Output gate 1L 1 3 4 ±20
D6 OG1 (R) Output gate 1R 1 3 4 ±20
B2 DD (L) Dump drain 22 24 26 -0.3 to +30
B7 DD (R) Dump drain 22 24 26 -0.3 to +30
D2 OG2 (L) Output gate 2L See Note 11 ±20
D7 OG2 (R) Output gate 2R See Note 11 ±20
B1 OD (L) Output drain L 27 29 32 -0.3 to +35
B8 OD (R) Output drain R 27 29 32 -0.3 to +35
A2 OS (L) Output source L See Note 12 -0.3 to +25
A7 OS (R) Output source R See Note 12 -0.3 to +25
C2 RD (L) Reset drain L 15 17 19 -0.3 to +25
C7 RD (R) Reset drain R 15 17 19 -0.3 to +25
Connections for optional U309 JFET (see note 13)
A3 RL (L) Load resistor L Analogue ground (0V)
A6 RL (R) Load resistor R Analogue ground(0V)
B3 OP (L) JFET source L
B6 OP (R) JFET source R
C3 JD ( L) JFET drain L OD (L)+2V
C6 JD ( R) JFET drain R OD (R)+2V
Optional connections (Temperature sensor- see Note 14)
D1, F1 Temp Temperature sensor Thermistor
E1 NC No Connection
If all voltages are set to the typical values, operation should be obtained at or close to the specifications, but some adjustment
within the minimum-maximum range specified may be required to optimise performance. Refer to the specific device test data
provided with each device as this gives the optimised values obtained during testing.