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© e2v technologies (uk) limited 2014 

Document subject to disclaimer on page 1 

A1A-100026 Version 9, page 2 

 

 

PERFORMANCE at 173 K 

Electro-Optical Specification (Note 1) 

 

Min 

Typical 

Max 

Units 

Note 

Peak charge storage (image) 

100k 

150k 

e

/pixel 

2a 

Peak charge storage (register) 

600k 

e

/pixel 

2b 

Output node capacity: 

OG2 low (mode 1) 
OG2 high (mode 2)

 

 


 

300k 

1,200k 

 


 

e

 

e

 

2c 

Output amplifier responsivity: 

OG2 low (mode 1) 
OG2 high (mode 2)

 

 

3.0 

 

4.5 
1.5 

 
 

µ

V/e

 

 

Read-out noise (mode 1) 

e

 rms 

Maximum read-out frequency 

MHz 

Dark signal  

Specified at 173K 

[Equivalent 153K value] 

 


 

 

 

182 

[1] 

e

/pixel/h 

Charge transfer efficiency: 
  parallel 
  serial 

 

99.999 
99.999 

 

99.9995 
99.9998 

 


 


 

 

NOTES 

1. 

Device performance will be within the limits specified by “max” and “min” when operated at the recommended voltages 
supplied with the test data and when measured at a register clock frequency in the range 0.1 – 1.0 MHz. Most tests are 
performed at a nominal 500 kHz pixel rate. The noise as specified is separately measured in accordance with note 4. 

2. 

(a) Signal level at which resolution begins to degrade. 

(b) Maximum register capacity. 

(c) Output node capacity under different modes. 

3. 

For highest responsivity and lowest nose (mode 1), the voltage on OG2 should be 1V higher than that on OG1. For 
increased charge handling capacity, but with higher noise (mode 2), the voltage on OG1 should stay the same but the 
voltage on OG2 should be taken to about 20V. 

4. 

Measured at OS with correlated double sampling at 20 kHz pixel rate in mode 1. 

5. 

Depending on the external load capacitance to be driven. Higher loads (> 20 pF) can benefit from use of the optional JFET 
buffer. The register will transfer charge at higher frequencies, but performance cannot be guaranteed. 

6. 

The dark signal is typically measured at a device temperature of 173K It is a strong function of temperature and the typical 
average (background) dark signal is taken as: 

Q

d

/Q

do

 = 122T³e 

-6400 /T 

where Q

do 

is the dark current at 293 K. 

Note that this is typical performance and some variation may be seen between devices. Dark current is lowest with the 
substrate voltage at +9 V, and somewhat higher with substrate at 0 V.  However, Vss=0V is now recommended for highest 
spatial resolution; see note 9 later.  

7. 

Measured with a 

55

Fe X-ray source. The CTE value is quoted for the complete clock cycle (i.e. not per phase). 

 

Summary of Contents for CCD42-90

Page 1: ...egister is designed to accommodate four image pixels of charge and a summing well is provided capable of holding that from six image pixels The output amplifier has a feature to enable the responsivit...

Page 2: ...grade b Maximum register capacity c Output node capacity under different modes 3 For highest responsivity and lowest nose mode 1 the voltage on OG2 should be 1V higher than that on OG1 For increased c...

Page 3: ...neration rate is 5 e pixel s at 173 K which is also equivalent to 100 e hour at 153 K The temperature dependence is the same as for the mean dark signal see note 6 above Black spots A black spot defec...

Page 4: ...band Deep depletion silicon Astro Midband Deep depletion silicon Astro ER1 response Deep depletion silicon Astro Multi 2 Maximum Pixel Response Non Uniformity PRNU 1 Wavelength nm Minimum QE Minimum Q...

Page 5: ...es of charges as they are transferred from the image section At either end of the register are an additional 50 elements leading to the charge detection amplifiers The last clocked electrodes are sepa...

Page 6: ...st applications the output at OS will be used with external load 1 that can be either a 3 5 mA current source or a 5 10 k resistor RL JD and OP and external load 2 are left unconnected In this mode th...

Page 7: ...1 3 4 20 B2 DD L Dump drain 22 24 26 0 3 to 30 B7 DD R Dump drain 22 24 26 0 3 to 30 D2 OG2 L Output gate 2L See Note 11 20 D7 OG2 R Output gate 2R See Note 11 20 B1 OD L Output drain L 27 29 32 0 3...

Page 8: ...wn For charge dumping DG should be pulsed to within 12 2 V 11 OG1 is typically set to 3 V Then for operation in the high responsivity low noise mode 1 OG2 should be set 1 V higher at typically 4 V For...

Page 9: ...te voltage starts to increase from zero It is also important to ensure that excess currents see Note 12 do not flow in the OS pins Such currents could arise from rapid charging of a signal coupling ca...

Page 10: ...Document subject to disclaimer on page 1 A1A 100026 Version 9 page 10 FRAME READOUT TIMING DIAGRAM DETAIL OF LINE TRANSFER I 1 I 2 I 3 R 1 R 2 R R 3 toi toi toi toi toi tdtr tdrt I 1 I 2 I 3 R 1 R 2 R...

Page 11: ...DETAIL OF OUTPUT CLOCKING tWX tdX Reset feed through Signal output Reset sampling window Signal sampling window Trr R 1 R 2 R R 3 Output tWX tdX Reset feed through Signal output Reset sampling window...

Page 12: ...read out R 1 tdrs tdg2 tdg3 tdg4 tdg1 tdsr Line transfer into register Dump charge into drain Next line read out Line transfer into register DETAIL OF VERTICAL LINE TRANSFER MULTIPLE LINE DUMP 1 2 R...

Page 13: ...clock cycle period 300 see Note 16 see Note 15 ns trr Register pulse rise time 10 to 90 50 0 1Tr 0 3Tr ns tfr Register pulse fall time 10 to 90 trr 0 1Tr 0 3Tr ns tor Register clock pulse overlap 50 0...

Page 14: ...gies uk limited 2014 Document subject to disclaimer on page 1 A1A 100026 Version 9 page 14 PACKAGE DETAIL Package Mass 150 g approx Inactive edge spacing Sides 260 50 m Top 120 50 m Bottom bond connec...

Page 15: ...GY RADIATION Performance parameters will begin to change if the device is subject to ionising radiation Characterisation data is held at e2v technologies with whom it is recommended that contact be ma...

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