e2v AT84CS001-EB, User Manual

Page: 8 / 39

Hardware Description
2-2 AT84CS001-EB Evaluation Kit User Guide
0904C–BDC–09/07
The board is 1.6 mm thick.
The digital data input, output and reset signals are located on the top metal layer.
The function signals are located on the top metal layer and layer 7.
The ground planes are located on layer 3 and 7.
Layer 5 is dedicated to the power supplies (3.3V, V
CCD
and V
PLUSD
).
2.2 Data and Clock
Input Accesses
Access to the digital data and clock inputs is provided by one female 2.54 mm pitch con-
nector (points) via 50
Ω
microstrip lines.
The connector is made of two rows:
„
The upper row is dedicated to the data and clock signals
„
The lower row is connected to ground
„
Each differential signal pair is separated by a connection to ground, as illustrated in
Figure 2-1
Figure 2-1. Input Data Connector
The input lines are matched (in length) within ±1 mm.
Note: 100
Ω
termination is provided on-chip.
2.3 Digital Output
Access to the digital data and clock outputs is provided by four male 2.54 mm pitch con-
nectors (points) via 50
Ω
microstrip lines.
The connector is made of two rows:
„
The upper row is dedicated to the data and clock signals
„
The lower row is connected to ground
Each output port is separated by a connection to ground, as illustrated in Figure 2-2 on
page 2-3.
GND I9 I9N GND GND I0 I0N GND
GND GND GND GND GND GND GND GND
IOR IORN GND
GND GND GND