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AT84CS001-EB Evaluation Kit User Guide

5-1

0904C–BDC–09/07

Section 5

Package Information

5.1

AT84CS001 Pinout (Bottom View)

Figure 5-1.

AT84CSO01 Pinout

SLEEP

A0N

A1N

A2N

A3N

A4N

A5N

A6N

A7N

A8N

A9N

AORN

B0N

B1N

B2N

B3N

B4N

ASYNCRST

VPLUSD

VCCD

VPLUSD

VCCD

VPLUSD

VCCD

VPLUSD

VCCD

B5N

B6N

VCCD

VPLUSD

VCCD

VPLUSD

VCCD

VPLUSD

VCCD

VPLUSD

B7N

B8N

B9N

VPLUSD

VCCD

DRN

DRTYPE

VPLUSD

C0N

C1N

VPLUSD

C2N

C3N

VPLUSD

C4N

VCCD

DGND

CLKTYPE

DACTRL

DAEN

BIST

VCCD

D9N

VPLUSD

D8N

D7N

VPLUSD

VCCD

D6N

D5N

VPLUSD

D4N

D3N

VPLUSD

D2N

D1N

VPLUSD

D0N

VPLUSD

C9N

VPLUSD

C8N

C7N

C5N

C6N

CLKDACTRL

IOR

DGND

N/C

DGND

DA0N

DAIN

I2N

VCCD

N/C

DGND

VPLUSD

DGND

I1N

I0N

DGND

STAGG

DA0

DAI

CLK

I5N

I6N

I7N

I4N

I9N

I8N

CLKN

I3N

IORN

VCCD

DGND

VCCD

DGND

VCCD

DGND

VCCD

DGND

VCCD

DGND

DRA

DRAN

AOR

DRB

BORN

DRBN

BOR

DRCN

COR

DRC

CORN

DRDN

DOR

DRD

DORN

19 18 17 16 15 14 13 12 11 10 9

Summary of Contents for AT84CS001-EB

Page 1: ...AT84CS001 EB Evaluation Board User Guide...

Page 2: ......

Page 3: ...2 6 DMUX Functions 3 2 7 Power Supplies 3 Section 3 Operating Characteristics 1 3 1 Introduction 1 3 2 Operating Procedure 1 3 3 Electrical Characteristics 2 Section 4 Application Information 1 4 1 In...

Page 4: ...ii AT84CS001 EB Evaluation Board User Guide 0904C BDC 09 07 Ordering Information 1 Section 7 Appendix 1 7 1 AT84CS001 EB Electrical Schematics 1 7 2 AT84CS001 EB Board Layers 5...

Page 5: ...0 bit 2 2 GHz DMUX device SMA connectors for the standalone delay cell inputs and outputs and for the reset input accesses and 2 54 mm pitch con nectors compatible with high speed acquisition system p...

Page 6: ...s are 220 mm x 230 mm The board comes fully assembled and tested with the AT84CS001 installed Figure 1 1 Simplified Schematics of the AT84CS001 EB Evaluation Board As shown in Figure 1 1 different pow...

Page 7: ...of the board s structure Table 2 1 Board Structure Layer Characteristics Layer 1 Copper layer Copper thickness 40 m Input and output signals traces 50 microstrip lines Layer 2 RO4003 dielectric layer...

Page 8: ...pper row is dedicated to the data and clock signals The lower row is connected to ground Each differential signal pair is separated by a connection to ground as illustrated in Figure 2 1 Figure 2 1 In...

Page 9: ...outputs are floating must be terminated by 100 termination 2 6 DMUX Functions Two potentiometers are provided for the DMUX input clock delay control CLKDACTRL and the standalone delay cell control DA...

Page 10: ...User Guide 0904C BDC 09 07 Each power supply is decoupled as close as possible to the AT84CS001 device by 10 nF in parallel with 100 pF surface mount chip capacitors Note The decoupling capacitors are...

Page 11: ...VCCD 3 3V VPLUSD 2 5V and 3 3V 2 Connect the clock input signals CLK CLKN This clock may be single ended or differential Use a low phase noise high frequency generator You should use an LVDS signal to...

Page 12: ...miting values referenced to GND 0V to be applied individually while other parameters are within specified operating conditions Long exposure to maximum rating may affect device reliability All integra...

Page 13: ...age VCCD 3 15 3 3 3 45 V Output power supply voltage VPLUSD 2 375 2 5 2 625 V Digital power supply current 1 2 mode 1 4 mode SLEEP mode Additional current with SDA enabled Additional current with BIST...

Page 14: ...VCCD 3 V Reset input ASYNCRST Logic compatibility LVCMOS CMOS Control input voltages Logic low Logic high Common mode VIL VIH VICM 0 1 5 1 4 1 2 3 3 V Table 3 3 Electrical Operating Characteristics C...

Page 15: ...ata to Data Ready propagation delay TD1 0 3 0 333 500 ps Data Ready to output data propagation delay TD2 0 3 0 333 500 ps Output data pipeline delay Synchronized 1 2 mode Synchronized 1 4 mode Stagger...

Page 16: ...Operating Characteristics 3 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Page 17: ...ta The input data I0 I0N I9 I9N and IOR IORN and clock CLK CLKN as well as the DAI DAIN input data of the standalone delay cell are LVDS compatible on chip 100 Figure 4 1 Input Data and Clock Signals...

Page 18: ...gnal in inactive mode Figure 4 3 ASYNCRST Function If the DRRB reset is also used we recommend to apply the asynchronous reset while the DRRB reset is active The first data is available at the device...

Page 19: ...CTRL Function 4 4 3 DACTRL A standalone delay cell is available input DAI DAIN output DAO DAON control DACTRL enable DAEN This cell allows you to delay the incoming signal DAI DAIN by approximately 25...

Page 20: ...ut Inactive normal mode BIST jumper ON No BIST jumper OUT CLKTYPE Input clock mode CLK data valid on each rising edge of the CLK CLKN signal CLK 2 data valid on both rising and falling edges of the CL...

Page 21: ...ormation AT84CS001 EB Evaluation Kit User Guide 4 5 0904C BDC 09 07 Figure 4 5 Jumper Positions of DMUX Functions Jumper ON Jumper OUT BIST BIST STAGG SLEEP CLKTYPE DAEN RS DRTYPE STAGG SLEEP CLKTYPE...

Page 22: ...4CS001 DEMUX AT84AS008 Power supplies GW PPT 0o C Balun MACOM H9 Acquisition board Power supplies GW PPT HP16500C analysis logic A B C D GPIB bus LabView Fs ADC sampling data Clock HP86665B sinewave s...

Page 23: ...D VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD DGND CLKTYPE DACTRL DAEN BIST VCCD D9N D9 VPLUSD VPLUSD D8 D8N D7N D7 VPLUSD VPLUSD VCCD D6 D6N D5N D5 VPLUSD VPLUSD D4 D4N D3N D3 VPLUSD VPLUSD D2 D2N D1N D1...

Page 24: ...8 N18 P18 Inverted phase digital input signal IORN B18 In phase digital input signal additional bit IOR B19 Inverted phase digital input signal for additional bit DAI T18 In phase input signal for sta...

Page 25: ...D6 D7 D8 D9 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 In phase digital outputs for port D D0 is the LSB D9 is the MSB D0N D1N D2N D3N D4N D5N D6N D7N D8N D9N W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Inverted pha...

Page 26: ...Evaluation Kit User Guide 0904C BDC 09 07 STAGG A17 Staggered output mode selection signal BIST V17 Built In Self Test selection signal NC C19 Leave floating Table 5 1 ASTS8CSO01 Pinout Description C...

Page 27: ...Package Information AT84CS001 EB Evaluation Kit User Guide 5 5 0904C BDC 09 07 5 2 Package Outline Figure 5 2 Package Outline Schematics...

Page 28: ...Package Information 5 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Page 29: ...Number Package Temperature Range Screening Comments AT84XCS001TP EBGA 240 Ambient Prototype Please contact your local sales office AT84CS001VTP EBGA 240 Industrial V grade 40 C TC TJ 110 C Standard AT...

Page 30: ...Ordering Information 6 2 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Page 31: ...AT84CS001 EB Evaluation Kit User Guide 7 1 0904C BDC 09 07 Section 7 Appendix 7 1 AT84CS001 EB Electrical Schematics Figure 7 1 Data I O Electrical Schematic...

Page 32: ...Appendix 7 2 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 2 Data I O Electrical Schematic 2 NC NC...

Page 33: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 3 0904C BDC 09 07 Figure 7 3 Electrical Schematic of Power Supplies 1...

Page 34: ...Appendix 7 4 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 4 Electrical Schematic of Power Supplies 2...

Page 35: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 5 0904C BDC 09 07 Figure 7 5 Electrical Schematic of Power Supplies 3...

Page 36: ...Appendix 7 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 7 2 AT84CS001 EB Board Layers Figure 7 6 Top Layer...

Page 37: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 7 0904C BDC 09 07 Figure 7 7 Bottom Layer Figure 7 8 Equipped Board Top...

Page 38: ...Appendix 7 8 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 9 Equipped Board Bottom...

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