Application Information
4-2
AT84CS001-EB Evaluation Kit User Guide
0904C–BDC–09/07
Figure 4-2.
Implementation of Differential Digital Outputs
4.4
DMUX Functions
4.4.1
ASYNCRST
The asynchronous reset is mandatory to start the device properly. It must be applied
after power up of the device and after any change of DMUX function.
A push button is provided to perform this reset and pull-up and pull-down resistors main-
tain the ASYNCRST signal in inactive mode.
Figure 4-3.
ASYNCRST Function
If the DRRB reset is also used, we recommend to apply the asynchronous reset while
the DRRB reset is active.
The first data is available at the device output after TOD + 7.5 cycles.
4.4.2
CLKDACTRL
A delay cell is provided to allow you to tune the delay between the clock and data at the
DMUX input. The delay is controlled via the CLKDACTRL potentiometer.
This cell allows you to delay the internal DMUX clock by approximately 250 ps via the
CLKDACTRL potentiometer (varying from V
CCD
/3 to (2 × V
CCD
)/3).
Di
DiN
100
Ω
5 0
Ω
line
DRN
DR
100
Ω
5 0
Ω
line
5 0
Ω
line
5 0
Ω
line
3.3V
GND
AT84CS001
3.3V
15 K
Ω
4.7 K
Ω
Summary of Contents for AT84CS001-EB
Page 1: ...AT84CS001 EB Evaluation Board User Guide...
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Page 16: ...Operating Characteristics 3 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...
Page 28: ...Package Information 5 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...
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