Specifications subject to change without notice
© Digital View Ltd
– Ver 2.0 August 19, 2016 (SVX-4096_manual.doc)
Page 23 of 54
The VR for brightness depends on the inverter. The main power load for On/Off is handled by a relay on the controller.
CP2 - Reserved
IR1
– Infra-Red sensor connector: JST B3B-XH-A (Matching type : XHP-3)
PIN
SYMBOL
DESCRIPTION
1
GND
Ground
2
VCC
+3.3V
3
IR Data
IR data
J1
– Ethernet connector: RJ-45 connector
PIN
SYMBOL
DESCRIPTION
1
TX+
Transmit data +
2
TX-
Transmit data -
3
RX+
Receive data +
4
CMT1
Network use
5
CMT1
Network use
6
RX-
Receive data -
7
CMT3
Network use
8
CMT3
Network use
J2
– LVDS_3 output connector: JAE FI-RE51S-HF (Matching type : JAE FI-RE51HL)
PIN
SYMBOL
DESCRIPTION
1
GND
Ground
2
LVDS_
Positive differential LVDS data bit D4
3
LVDS_OUT3_D4-
Negative differential LVDS data bit D4
4
LVDS_
Positive differential LVDS data bit D3
5
LVDS_OUT3_D3-
Negative differential LVDS data bit D3
6
LVDS_
Positive LVDS clock for D channel
7
LVDS_OUT3_DC-
Negative LVDS clock for D channel
8
LVDS_
Positive differential LVDS data bit D2
9
LVDS_OUT3_D2-
Negative differential LVDS data bit D2
10
LVDS_
Positive differential LVDS data bit D1
11
LVDS_OUT3_D1-
Negative differential LVDS data bit D1
12
LVDS_
Positive differential LVDS data bit D0
13
LVDS_OUT3_D0-
Negative differential LVDS data bit D0
14
LVDS_
Positive differential LVDS data bit C4
15
LVDS_OUT3_C4-
Negative differential LVDS data bit C4
16
LVDS_
Positive differential LVDS data bit C3
17
LVDS_OUT3_C3-
Negative differential LVDS data bit C3
18
LVDS_
Positive LVDS clock for C channel
19
LVDS_OUT3_CC-
Negative LVDS clock for C channel
20
LVDS_
Positive differential LVDS data bit C2
21
LVDS_OUT3_C2-
Negative differential LVDS data bit C2
22
LVDS_
Positive differential LVDS data bit C1
23
LVDS_OUT3_C1-
Negative differential LVDS data bit C1
24
LVDS_
Positive differential LVDS data bit C0
25
LVDS_OUT3_C0-
Negative differential LVDS data bit C0
26
GND
Ground
27
LVDS_
Positive differential LVDS data bit B4
28
LVDS_OUT3_B4-
Negative differential LVDS data bit B4
29
LVDS_
Positive differential LVDS data bit B3
30
LVDS_OUT3_B3-
Negative differential LVDS data bit B3
31
LVDS_
Positive LVDS clock for B channel
32
LVDS_OUT3_BC-
Negative LVDS clock for B channel
33
LVDS_
Positive differential LVDS data bit B2
34
LVDS_OUT3_B2-
Negative differential LVDS data bit B2
35
LVDS_
Positive differential LVDS data bit B1
36
LVDS_OUT3_B1-
Negative differential LVDS data bit B1
37
LVDS_
Positive differential LVDS data bit B0
38
LVDS_OUT3_B0-
Negative differential LVDS data bit B0
39
LVDS_
Positive differential LVDS data bit A4
40
LVDS_OUT3_A4-
Negative differential LVDS data bit A4
41
LVDS_
Positive differential LVDS data bit A3
42
LVDS_OUT3_A3-
Negative differential LVDS data bit A3
43
LVDS_
Positive LVDS clock for A channel
44
LVDS_OUT3_AC-
Negative LVDS clock for A channel
45
LVDS_
Positive differential LVDS data bit A2
46
LVDS_OUT3_A2-
Negative differential LVDS data bit A2
47
LVDS_
Positive differential LVDS data bit A1
48
LVDS_OUT3_A1-
Negative differential LVDS data bit A1
49
LVDS_
Positive differential LVDS data bit A0
50
LVDS_OUT3_A0-
Negative differential LVDS data bit A0
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