Digital Spectrum TMS320C6413, Technical Reference

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Spectrum Digital, Inc
2-9
2.3 Synchronous DRAM
The EVM uses an industry standard 64 megabit Synchronous SDRAM. It uses a 32-bit
interface and is used with up a maximum 100 MHz. memory clock. Since the DSP runs
at 500 or 600 MHz, the EMIF must be programmed to use the SDRAM at a divider of
the core clock rate or use the alternate EMIF Clock input.
The SDRAM occupies chip enable 0.
SDRAM must be constantly refreshed to maintain the integrity of its contents. This
SDRAM must update one row every 15.6 microseconds to meet its minimum
requirements. The EMIF can be programmed to automatically generate refresh signals
based on this time period.
2.4 Flash Memory
The EVM provides two devices each consisting of 256K x 16-bit words of external
Flash memory. The board itself is pinned out to allow expansion to 1M 32 bit words.
Typically the Flash is mapped into CE1 space because that is where the bootloader
looks for a boot image when booting from the Flash. Because the bootloader default
configuration is 8 bit boot mode usually only the Flash on D0-D7 is used. The CE1
space is shared by the CPLD, UART, and the Flash, but the CPLD timings are
subsetted by the Flash so the Flash is the critical factor in configuring CE1.
The Flash itself is a 70ns device but some additional delays are incurred in the CPLD
logic that separates the Flash and CPLD registers. Because of this, the EMIF should
be programmed for an access time of at least 80ns, and typically 100 ns.
2.5 SBRAM Memory
The EVM has 1 megabyte of SBRAM optionally mapped in CE3 space. If the SBRAM is
not used CE3 can be used for expansion daughter card accesses by disabling the
secondary chip select on the SBRAM via the Board Register in the CPLD.
2.6 LEDs and DIP Switches
The EVM includes 4 software accessible LEDs (DS1-DS4) and DIP switches (S2) that
provide the user a simple form of input/output. Both are accessed through the CPLD
USER_REG register.