Pmod CAN Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page
3
of
8
Header J3
Pin
Signal
Description
1
CANL
CAN Low-Level Voltage I/O
2
CANH
CAN High-Level Voltage I/O
3
GND
Power Supply Ground
Jumpers
Pin
Signal
Description
JP1
Loaded/ Unloaded
End of bus terminated with a combined 120Ω impedance/ Do not
terminate the end of the bus
JP2
Loaded/ Unloaded
Terminate the CAN bus lines with a capacitor to ground/ No termination
1.2 Physical Dimensions
The pins on the pin header are spaced 100 mil apart. The PCB is 1.8 inches long on the sides parallel to the pins on
the pin header and 1.4 inches long on the sides perpendicular to the pin header.
2
Functional Description
to enable CAN communication with a variety of external devices.
A complete CAN solution with a controller and transceiver can be implemented on a system board by
communicating with the host board via the
in SPI mode 0 or 3. The two differential lines on the
transceiver, CANH and CANL, enable balanced differential signaling to eliminate most of the electromagnetic field
(EMF) and provide high noise immunity within the system.
2.1 Serial Communication
The Pmod CAN communicates with the host board via the SPI protocol. By driving and keeping the Chip Select line
(pin 1) at a logic level low, users may communicate back and forth with the Pmod depending on whether or not
both sets of data lines are enabled. The embedded chip on the Pmod operates in SPI Mode 0 or 3, with data
captured on the rising edge of the clock and data transferred on the falling edge of the clock, and a minimum clock
cycle time of 100 nanoseconds as per Table 7-6 (page 70) of the
Nine SPI instructions are available to read the status of the receiver, load a transmit buffer, modify bits in a register
and more. Most of the instruction commands are single byte instructions followed by an address byte. More
information is available in the Quick Start section as well as Section 5 (page 55) of the MCP25625 datasheet.
2.2 Register Details
2.2.1 CANINTE
The CANINTE register (page 51) enables the generation of interrupts on Pin 7.
