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Nexys4 DDR™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating
the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the
process.
For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions
User Guide (ug586)
1
.
4.2 Quad-SPI Flash
FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and mode
settings are available to cause the FPGA to automatically read a configuration from this device at power on. An
Artix-7 100T configuration file requires just less than four MiB (mebibyte) of memory, leaving about 77% of the
flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory
can be used for custom data.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation
of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose
user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after
configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2.
NOTE: Refer to the manufacturer’s data sheets
2
and Xilinx user guides
3
for more information.
CS#
SDI/DQ0
SDO/DQ1
E9
K18
K17
L13
SPI Flash
WP#/DQ2
HLD#/DQ3
L14
M14
SCK
Artix-7
SPI Flash
Figure 4. Nexys4 DDR SPI flash pin-out.
5
Ethernet PHY
The Nexys4 DDR board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8720A) paired with an RJ-
45 Ethernet jack with integrated magnetics. The SMSC PHY uses the RMII interface and supports 10/100 Mb/s.
Figure 5 illustrates the pin connections between the Artix-7 and the Ethernet PHY. At power-on reset, the PHY is
set to the following defaults:
RMII mode interface
Auto-negotiation enabled, advertising all 10/100 mode capable
PHY address=00001
1
http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf
2
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
3
http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf