Digilent Nexys 4 Reference Manual Download Page 11

Nexys4 DDR™ FPGA Board Reference Manual 

 

 

Copyright Digilent, Inc. All rights reserved. 

Other product and company names mentioned may be trademarks of their respective owners.

 

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Artix-7

F4

PIC24FJ128

PS2_CLK

B2

HOST (J5)

2

PS2_DAT

FPGA 

Config

microSD

7

FPGA 
Config

User I/O

SD MICRO (J1)

SD/USB (JP2)

 

Figure 7. Nexys4 DDR PIC24 connections.

 

8.1  HID Controller 

The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 
bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use 
existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to 
communicate with a host. On the Nexys4 DDR, the microcontroller emulates a PS/2 device while the FPGA plays 
the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB 
first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-
directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in 
Figure 8. 

T

CK

T

SU

Clock time
Data-to-clock setup time

30us

5us

50us
25us

Symbol

Parameter

Min

Max

T

HLD

Clock-to-data hold time

5us

25us

Edge 0

‘0’ start bit

‘1’ stop bit

Edge 10

Tsu

T

hld

Tck Tck

CLOCK

DATA

 

Figure 8. PS/2 device-to-host timing diagram. 

The clock and data signals are only driven when data transfers occur; otherwise, they are held in the idle state at 
high-impedance (open-drain drivers). This requires that when the PS/2 signals are used in a design, internal pull-
ups must be enabled in the FPGA on the data and clock pins. The clock signal is normally driven by the device, but 
may be held low by the host in special cases. The timings define signal requirements for mouse-to-host 
communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the 
FPGA to create a keyboard or mouse interface. 

When a keyboard or mouse is connected to the Nexys4 DDR, a “self-test passed” command (0xAA) is sent to the 
host. After this, commands may be issued to the device. Since both the keyboard and the mouse use the same 
PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID 
command (0xF2). Also, a mouse sends its ID (0x00) right after the “self-test passed” command, which distinguishes 
it from a keyboard. 

Summary of Contents for Nexys 4

Page 1: ...h performance logic and offers more capacity higher performance and more resources than earlier designs Artix 7 100T features include 15 850 logic slices each with four 6 input LUTs and 8 flip flops 4...

Page 2: ...nal Pmod port XADC 4 Pmod port s 16 Programming mode jumper 5 Microphone 17 Audio connector 6 Power supply test point s 18 VGA connector 7 LEDs 16 19 FPGA programming done LED 8 Slide switches 20 Ethe...

Page 3: ...ource is used All Nexys4 DDR power supplies can be turned on and off by a single logic level power switch SW16 A power good LED LD22 driven by the power good output of the ADP2118 supply indicates tha...

Page 4: ...speed designs Supply Circuits Device Current max typical 3 3V FPGA I O USB ports Clocks RAM I O Ethernet SD slot Sensors Flash IC17 ADP2118 3A 0 1 to 1 5A 1 0V FPGA Core IC22 ADP2118 3A 0 2 to 1 3A 1...

Page 5: ...can take a long time to transfer The time it takes to program the Nexys4 can be decreased by compressing the bitstream before programming and then allowing the FPGA to decompress the bitstream itself...

Page 6: ...3 Programming files stored in the flash device will remain until they are overwritten regardless of power cycle events Programming the flash can take as long as four to five minutes which is mostly du...

Page 7: ...are outlined below and differ in complexity and design flexibility The straightforward way is to use the Digilent provided DDR to SRAM adapter module which instantiates the memory controller and uses...

Page 8: ...in commands on the SPI bus The implementation of this protocol is outside the scope of this document All signals in the SPI bus except SCK are general purpose user I O pins after FPGA configuration SC...

Page 9: ...oller IP core NOTE Refer to the LAN8720A data sheet4 for further information C11 C9 A9 Artix 7 B3 RESET INT REFCLK0 CRS_DV MODE2 TXEN MDIO 4 MDC D10 B8 D9 RXD1 MODE1 TXD0 SMSC LAN8720A RJ 45 with magn...

Page 10: ...of one another Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers and vice...

Page 11: ...us timings are shown in Figure 8 TCK TSU Clock time Data to clock setup time 30us 5us 50us 25us Symbol Parameter Min Max THLD Clock to data hold time 5us 25us Edge 0 0 start bit 1 stop bit Edge 10 Tsu...

Page 12: ...11 Ctrl E0 14 F1 05 F2 06 F3 04 F4 0C F5 03 F6 0B F7 83 F8 0A F9 01 F10 09 F11 78 F12 07 Figure 9 Keyboard scan codes A host device can also send data to the keyboard Table 3 shows a list of some com...

Page 13: ...g the XV and YV bits in the status byte are movement overflow indicators A 1 means overflow has occurred If the mouse moves continuously the 33 bit transmissions are repeated every 50ms or so The L an...

Page 14: ...0 RED1 RED2 4KW 2KW 1KW GRN0 GRN1 GRN2 RED GRN BLU HS VS Artix 7 A3 B4 C5 B11 C6 A5 B6 B12 HSYNC VSYNC 510W RED3 A4 510W GRN3 A6 4KW 2KW 1KW BLU0 BLU1 BLU2 510W BLU3 B7 C7 D7 D8 9 1 VGA System Timing...

Page 15: ...ected by these magnetic fields Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a raste...

Page 16: ...0 1Hz refresh the signal timings shown in Figure 14 can be derived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which in...

Page 17: ...lor LEDs sixteen slide switches six push buttons sixteen individual LEDs and an eight digit seven segment display as shown in Figure 16 The pushbuttons and slide switches are connected to the FPGA via...

Page 18: ...LEDs AN3 AN2 AN1 AN0 L16 J15 H17 K15 J13 N14 R18 V17 U17 U16 J14 T9 J18 J17 T10 R10 K16 K13 P15 T11 L18 CA CB CC CD CE CF CG DP H15 7 seg Display Slide Switches 3 3V Buttons N17 BTNC R16 T13 H6 U12 U1...

Page 19: ...illumination patterns corresponding to decimal digits The anodes of the seven LEDs forming each digit are tied together into one common anode circuit node but the LED cathodes remain separate as show...

Page 20: ...r 4ms in an endless succession the display will show 71 in the first two digits An example timing diagram for a four digit controller is shown in Figure 19 AN0 AN1 AN2 AN3 Cathodes Digit 0 Refresh per...

Page 21: ...collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready made functions like A D s D A s motor drivers sensors as well as other functions See www digilentinc c...

Page 22: ...he SPI is also available if needed Once control over the SD bus is passed from the microcontroller to the FPGA the SD_RESET signal needs to be actively driven low by the FPGA to power the microSD card...

Page 23: ...nd CT pins refer to the ADT7420 datasheet 13 3 Quick Start Operation When the ADT7420 is powered up it is in a mode that can be used as a simple temperature sensor without any initial configuration By...

Page 24: ...rometer Access accelerometer data by reading the device registers For a full list of registers their functionality and communication specifications refer to the ADXL362 datasheet5 14 2 Interrupts Seve...

Page 25: ...d circuit of delta sigma modulator is shown in Figure 26 Integral PDM Analog clk Flip Flop Figure 26 Simple delta sigma modulator circuit Sum Integrator Out Flip flop Output 0 4 0 0 4 0 0 4 0 4 0 0 4...

Page 26: ...24 KHz there can be two counters that count 128 samples at 12 KHz as shown in Figure 28 128 Samples 53 3ns 128 Samples 128 Samples Counter 1 Counting Counter 1 Counting Counter 2 Counting 41 6ns 0 41...

Page 27: ...s a chain of pulses at some fixed frequency with each pulse potentially having a different width This digital signal can be passed through a simple low pass filter that integrates the digital waveform...

Page 28: ...bitstream for this design are available for download from the Digilent website If the demo configuration is present in the flash and the Nexys4 DDR board is powered on in SPI mode the demo project wil...

Page 29: ...ay be trademarks of their respective owners Page 29 of 29 Stressed solder joints can be repaired by reheating and reflowing solder and contaminants can be cleaned with off the shelf electronics cleani...

Page 30: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 292P KIT 410 292...

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