Nexys4 DDR™ FPGA Board Reference Manual
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The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will
turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible
indicate power-on, FPGA programming status, and USB and Ethernet port status.
10.1 Seven-Segment Display
The Nexys4 DDR board contains two four-digit common anode seven-segment LED displays, configured to behave
like a single eight-digit display. Each of the eight digits is composed of seven segments arranged in a “figure 8”
pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128
patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in
Figure 17. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.
Figure 17. An un-illuminated seven-segment display and nine illumination patterns corresponding to decimal digits.
The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the
LED cathodes remain separate, as shown in Fig 18. The common anode signals are available as eight “digit enable”
input signals to the 8-digit display. The cathodes of similar segments on all four displays are connected into seven
circuit nodes labeled CA through CG. For example, the eight “D” cathodes from the eight digits are grouped
together into a single circuit node called “CD.” These seven cathode signals are available as inputs to the 8-digit
display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all
digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted.
To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the
Nexys4 DDR uses transistors to drive enough current into the common anode point, the anode enables are
inverted. Therefore, both the AN0..7 and the CA..G/DP signals are driven low when active.
A
F
E
D
C
B
G
Common anode
Individual cathodes
DP
AN3
AN2
AN1
AN0
CA CB CC CD CE CF CG DP
Eight-digit Seven
Segment Display
AN7
AN6
AN5
AN4
CA CB CC CD CE CF CG DP
Figure 18. Common anode circuit node.
