NetFPGA-SUME™ Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page
17
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18
Clock Name
Source
Destination
Frequency
Common Useage
FPGA_SYSCLK
IC16 DSC1103,
IC17 SI5330
FPGA (H19, G18)
200MHz
General Purpose
QDRII_SYSCLK
IC16 DSC1103,
IC17 SI5330
FPGA (AD32, AD33)
200MHz
Used by MIG for QDRIIA,
QDRIIB
QDRIIC_SYSCLK
IC16 DSC1103,
IC17 SI5330
FPGA (AU14, AU13)
200MHz
Used by MIG for QDRIIC
SATA_SYSCLK
IC21 DSC1103
FPGA
(MGTREFCLK0_116:T8, T7)
150MHz
Used by SATA
transceivers (Bank 116
Lane 0/1)
SFP_CLK
IC20 SI5324
FPGA (MGTREFCLK0_118:
E10, E9)
156.25MHz
(Configurable)
Shared by transceivers
of SFP+ and QTH
DDR3_SYSCLK
IC18 DSC1103
FPGA (E34, E35)
233.33MHz
Shared by MIG for
DDR3A, DDR3B
PCIE-CLK
PCI-E Connector
FPGA (MGTREFCLK1_115:
AB8, AB7)
100MHz
Used by PCI-Express
Core
FMC_GBT_CLK0 FMC Connector
FPGA (MGTREFCLK0_112:
AT8, AT7)
-
Used by FMC
transceivers (Bank 111,
112, 113)
FMC_GBT_CLK1 FMC Connector
FPGA (MGTREFCLK1_112:
AU10, AU9)
-
Used by FMC
transceivers (Bank 111,
112, 113)
FMC_CLK0
FMC Connector
FPGA (AR27, AT27)
-
Used by FMC card
FMC_CLK1
FMC Connector
FPGA (AV34, AV35)
-
Used by FMC card
6
Expansion Interfaces
6.1 FMC
The NetFPGA-SUME board includes a VITA-57 compatible FMC (FPGA Mezzanine Card) carrier connector. A High
Pin Count (HPC) connector is used to provide the maximum possible compatibility with a variety of commercially
available mezzanine cards. Select I/O ports on the XC7V690T are connected to all of the standard Low Pin Count
(LPC) signals on the connector, due to the limitations of the FFG1761 package. All the I/O ports connected to FMC
connector only supports 1.8V logic. All 10 differential send/receive pairs for GTX transceivers are also supported.
Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard
for additional details regarding standard FMC module and carrier requirements. Refer to Appendix B of this
document for specific I/O constraints relating FPGA pins to their associated FMC control and connector pins.
6.2 QTH
The NetFPGA-SUME board includes a Samtec 0.5 mm-pitch QSH/QTH family of high-speed board-to-board
communication. The QTH connector wires out 8 transceivers from Virtex-7 FPGAs and tested at a speed of
12.5Gbps. Please refer to
Samtec website
for additional details regarding the QTH connector's specification,
footprint, etc.
6.3 Pmod
The NetFPGA-SUME board also provides a Pmod port for peripheral extension. The Pmod port is arranged as a 2×6
vertical, 100-mil female connector that mates with standard 2×6 pin headers. Each 12-pin Pmod port provides two
