NetFPGA-SUME™ Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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5.2 MicroSD Card
The microSD card connector on NetFPGA-SUME board provides a removable non-volatile storage resource. This
connector supports a micro-SD memory card and meets all physical layer requirements of both SPI and SD bus
protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at 3.3V
to support SC, HC, and XC class SD cards. Please see
SD Specifications Part 1 Physical Layer Simplified Specification
by the Technical Committee of the SD Card Association for more details regarding the use of SD memory cards
with this connector.
5.3 SATA
The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers
(Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera
DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver
Wizard. Please refer to
Xilinx Answer Record AR 53364
,
AR 44587
and
UG769 7 Series FPGAs Transceivers Wizard
v2.6 User Guide
for more information.
5.4 PCI Express
The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor
motherboards. Eight of the FPGA's high speed serial GTX transceivers are dedicated to implementing eight-lanes of
Gen. 3.0 (8
GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4
configuration). These transceivers work in conjunction with the on-chip 7-Series Integrated PCI Express Block and
synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx
7-Series FPGAs Integrated Block for PCI Express V2.0
(PG054) product guide and
7-Series FPGAs GTX/GTH
Transceivers
(UG476) user guide for more information.
5.5 SFP+ 10Gbps Ethernet Interface
The NetFPGA-SUME board provides four enhanced small form factor pluggable (SFP+) connectors, each supports
10Gbps. Four of the FPGA's high speed serial GTX transceivers on Bank 119 are dedicated to four SFP+ ports. These
connectors are capable of implementing 10GBase-SR/LR Ethernet Protocols.
5.6 I2C
The architecture of Inter-Integrated Circuit (I
2
C) buses on the NetFPGA-SUME board is illustrated in the figure
below.
