An external power supply can be used by plugging it into the power jack (J27). The supply must use a coax, center-positive
2.1mm internal-diameter plug, and deliver 12VDC ±5 %. The minimum current rating of the supply depends on the actual
design implemented in the FPGA, but at least 3A (i.e., at least 36W) is recommended. For high-power FMC applications a 60W
supply is recommended.
Voltage regulator circuits from Linear Technology create the different voltages required by the FPGA and on-board peripherals
from the main power input. Some regulators use the outputs of another regulator as input, depending on design considerations.
In some cases this chaining helps in creating the proper power-on sequence for circuits. In other cases the chaining of power
supply enables achieves the same purpose.
Table 2 provides information on maximum and typical currents for each power rail. The typical currents strongly depend on
FPGA configuration and the values provided are the current consumption of the OOB demo.
Supply Circuits
Device
Current
(max/typical)
3.3 V
FPGA I/O, USB, FMC, Clocks, Pmod, Ethernet, SD slot,
Flash, DisplayPort, HDMI
IC42:
LTC3855#1
6 A / 0.8 A
1.0 V
FPGA Core
IC30: LTC3866
14 A / 1.2 A
1.8 V
FPGA Auxiliary
IC36: LTC3605
5 A / 1.6 A
1.5 V
DDR3 and FPGA I/O
IC32: LTC3618
2 A / 0.7 A
0.75V
DDR3 termination, reference
IC32: LTC3618
2 A
2.0 V
FPGA Auxiliary I/O for memory high data rates
IC38: LT1762
150 mA
VADJ
(1.2-3.3 V)
User I/O, FMC and FPGA I/O
IC37: LTM4618 5A
3.3 V
Audio analog supply
IC12: LT1761
100 mA
5.0 V
USB Host, HDMI
IC42:
LTC3855#2
3 A / 0.3 A
MGT 1.0 V
Gigabit Transceivers VCC ()
IC41: LT3083
2 A
MGT 1.2 V
Gigabit Transceivers VTT
IC39: LTC3026
1.5 A
MGT 1.8 V
Gigabit Transceivers AUX
IC40: LT1762
150 mA
XADC 1.8 V
XADC supply
IC47: LT1761
100 mA
XADC 1.25 V XADC reference
IC48: LT1790
5 mA
Table 2. Voltage rail power settings.
The VADJ power rail requires special attention. It is an adjustable rail that powers the FMC mezzanine connector, user push-
buttons, switches, XADC Pmod connector and the FPGA banks connected to these peripherals (banks 15, 16, 17). The
feedback pin of the VADJ regulator is connected to a resistor network modifiable by jumper JP6. Changing its position
changes the resistor divider in the feedback loop, thereby changing the voltage on the regulator’s output. The possible voltages
2)
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