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Digilent Genesys 2, Reference Manual

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Digilent Genesys 2 Reference Manual Download Page 31

Start-up sequence: 

1. Power up VDD by pulling OLED ()_VDD low. Wait 1ms.
2. Pulse RES# low for at least 3us.
3. Send initialization/configuration commands (see Table 17).
4. Power up VBAT by pulling OLED ()_VBAT low. Wait 100ms for voltage to stabilize.
5. Clear screen by writing zero to the display buffer.
6. Send “Display On” command (0xAF).

Command function 

Command bytes 

Charge pump enable 

0x8D, 0x14 

Set pre-charge period 

0xD9, 0xF1 

Contrast control 

0x81, 0x0F 

Column inversion disable 

0xA0 

Scan direction 

0xC0 

COM pins configuration 

0xDA, 0x00 

Page 31 of 35

Summary of Contents for Genesys 2

Page 1: ...x part number XC7K325T 2FFG900C fast external memories high speed digital video ports and wide expansions options make the Genesys 2 well suited for data and video processing applications Several buil...

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Page 5: ...to 10 3125Gbps gigabit transceivers 1800Mbps DDR3 data rate with 32 bit data width Commercial 2 speed grade Fully bonded 400 pin FMC HPC connector USB UART Bridge 8 user switches 6 buttons OLED VGA c...

Page 6: ...e Vivado Design Suite as well as the ISE toolset Included in the box is a voucher that unlocks the Design Edition of Vivado that is device locked to the Genesys 2 This allows designs to be implemented...

Page 7: ...nnector 21 VGA connector 22 HDMI source connector 23 FPGA configuration source jumper 24 HDMI sink connector 25 Power switch 26 Power jack 12VDC Table 1 Genesys 2 features and connectors The Genesys 2...

Page 8: ...s 60 C and stops when it drops back to 40 C To develop new FPGA designs for the Genesys 2 download and install the Xilinx Vivado Design Suite http www xilinx com products design tools vivado html The...

Page 9: ...USB FMC Clocks Pmod Ethernet SD slot Flash DisplayPort HDMI IC42 LTC3855 1 6 A 0 8 A 1 0 V FPGA Core IC30 LTC3866 14 A 1 2 A 1 8 V FPGA Auxiliary IC36 LTC3605 5 A 1 6 A 1 5 V DDR3 and FPGA I O IC32 LT...

Page 10: ...Power monitoring circuit parameters The configuration and calibration registers are volatile so they need to be initialized after power up After initialization is done voltage current and power value...

Page 11: ...actual usage the fan might not be needed at all In this case the enable signal can be used to stop the fan and start it when the FPGA internal temperature as read by the XADC gets above a certain lim...

Page 12: ...SB mass storage device configuration modes already operate at their maximum possible speed After being successfully programmed the FPGA will cause the DONE LED LD14 to illuminate Pressing the PROG but...

Page 13: ...e 3 Attach the storage device to the Genesys 2 4 Set the JP5 Programming Mode jumper on the Genesys 2 to USB SD 5 Select the desired storage device using JP4 6 Push the PROG button or power cycle the...

Page 14: ...atio 4 1 VCCAUX_IO 2 0V Memory type Components Memory part MT41J256M16XX 107 Memory voltage 1 5V Data width 32 Data mask Enabled Input clock period 5004ps 200MHz Output driver impedance RZQ 7 Chip Sel...

Page 15: ...board includes a Realtek RTL8211E VL PHY paired with an RJ 45 Ethernet jack with integrated magnetics to implement a 10 100 1000 Ethernet port for network connection The PHY interfaces with the FPGA...

Page 16: ...nnected to MRCC GPIO pins AD12 AD11 in bank 33 This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a des...

Page 17: ...FT232R and the FPGA are shown in Figure 8 The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design Both of the interfaces have a software comp...

Page 18: ...y the USB controller read transfer When high the bus is driven by the FPGA write transfer CLKO Input 60 MHz clock used in synchronous mode Data is launched and can be captured on the rising edge Table...

Page 19: ...are organized differently and the keyboard interface allows bi directional data transfers so the host device can illuminate state LEDs on the keyboard Bus timings are shown in Figure 11 The clock and...

Page 20: ...data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by 8 bits of scan code LSB first followed by an odd parity bit and terminated w...

Page 21: ...en the fixed USB roles of the Genesys2 are not enough an on board USB 2 0 transceiver PHY provides physical layer implementation for any USB 2 0 user application It connect to a USB A J7 bottom row an...

Page 22: ...gned to a pushbutton or slide switch was inadvertently defined as an output The five pushbuttons arranged in a plus sign configuration are momentary switches that normally generate a low output when t...

Page 23: ...12 pin Pmod connector provides two power pins 6 and 12 two ground pins 5 and 11 and eight logic signals as shown in Figure 20 The VCC and Ground pins of can deliver up to 1A of current per pin Pin ass...

Page 24: ...JD7 JXADC7 A14 JA8 C17 JB8 R16 JC8 E6 JD8 JXADC8 A16 JA9 D18 JB9 T9 JC9 J2 JD9 JXADC9 B17 JA10 E18 JB10 U11 JC10 G6 JD10 JXADC10 A18 Table 11 Genesys 2 Pmod pin assignments Digilent produces a large c...

Page 25: ...d future FMC modules The Genesys 2 opens the door to the full range of I O standards supported by the Kintex 7 HR High Range I O architecture over the FMC connector The pin out of the FMC connector ca...

Page 26: ...3 Quad 116 pinout Quad Primitive Pin type Pin FMC signal 117 GTXE2_ CHANNEL X0Y8 MGTXTXP N0 K2 K1 DP8_C2M_P N MGTXRXP N0 K6 K5 DP8_M2C_P N X0Y9 MGTXTXP N1 J4 J3 DP9_C2M_P N MGTXRXP N1 H6 H5 DP9_M2C_P...

Page 27: ...5 input Both ports use HDMI type A receptacles and include HDMI buffer TMDS141 The buffers work by terminating equalizing conditioning and forwarding the HDMI stream between the connector and FPGA pin...

Page 28: ...1 3 http www hdmi org or later specifications for more information DisplayPort is a relatively new industry standard for digital display technology Its advantages over existing technologies are higher...

Page 29: ...ry channel is a bidirectional LVDS bus Depending on the Xilinx tool IP version instantiating a differential I O buffer with LVDS signaling standard might not be possible The work around is to have two...

Page 30: ...ires in controller terminology are CS D C SDIN and SCLK but CS is hard wired to ground This adds to the reset and two power control signals for proper start up sequencing The signals are summarized in...

Page 31: ...VBAT by pulling OLED _VBAT low Wait 100ms for voltage to stabilize 5 Clear screen by writing zero to the display buffer 6 Send Display On command 0xAF Command function Command bytes Charge pump enabl...

Page 32: ...sizing the right frequency from the on board 100 MHz reference oscillator For proper use the concept of audio paths needs to be understood Internal to the codec there are two signal paths Playback and...

Page 33: ...eference digilentinc com tag reference do showtag tag reference programmable logic https reference digilentinc com tag programmable logic do showtag tag programmable logic genesys 2 https reference di...

Page 34: ...https twitter com digilentinc https www facebook com Digilent https www youtube com user DigilentInc https instagram com digilentinc https github com digilent Connect With Us Page 34 of 35...

Page 35: ...eddit com r digilent https www linkedin com company 1454013 https www flickr com photos 127815101 N07 Page 35 of 35 11 9 2016 https reference digilentinc com reference programmable logic genesys 2 ref...

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