Non-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written to it, and
mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. A Kintex-7
325T configuration file requires just over 10 MiB (mebibyte) of memory, leaving about 70% of the flash device available for
user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this
protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after
FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is
provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is recommended for easy access
to the Flash memory.
NOTE: Refer to the manufacturer’s
datasheets
(http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf)
and
Xilinx
user guides
(http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf)
for more
information.
The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to
implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and
MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary interrupt (INTB), power
management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both of these signals are open-drain outputs from the
PHY and need internal pull-ups enabled in the FPGA, if they are used. The reset signal (PHYRSTB) is wired to bank 12,
powered at 3.3V. The connection diagram can be seen on Figure 7.
At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis:
• Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0])
• PHY address=00001 (PHY_AD[2:0])
• No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)
If an Ethernet cable is plugged in, establishing link is attempted straight after power-up, even if the FPGA is not programmed.
Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD10) and valid link state (LD9). The
table below shows the default behavior.
Function Designator State
Description
ACT LD10 Blinking
Transmitting or receiving
LINK LD9
On
Link
up
Blinking 0.4s ON, 2s OFF
Link up, Energy Efficient Ethernet (EEE) mode
Table 5. Ethernet status LEDs.
7. Ethernet PHY
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