Counter/Timer and DIO Control: Base+10 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
FREQ12
FREQ0
OUT2EN
OUT0EN
RSVD
GT0EN
SRC0
GT12EN
FREQ12
Input frequency select for the counter 1-2 cascade:
1 = Input to counter 1 is a 100KHz (one hundred, not ten) frequency derived from the on-board
10MHz oscillator.
0 = Input to counter 1 is 10MHz from the on-board oscillator.
FREQ0
Input frequency select for counter 0 when SRC0 = 1 (bit 1):
1 = Input to counter 0 is a 10KHz (ten, not one hundred) frequency derived from the on-board 10MHz
oscillator.
0 = Input to counter 0 is 10MHz from the on-board oscillator.
OUT2EN
Counter/timer 2 output enable:
1 = Counter 2 output appears on I/O header CN12, pin 28.
0 = CN12, pin 28, is controlled by bit DOUT0 at Base+1.
OUT0EN
Counter/timer 0 output enable:
1 = Counter 0 output appears on I/O header CN12 pin 27, OUT 0 / DOUT 0.
0 =.OUT 0 / DOUT 0 pin is set by bit DOUT0 at Base+1.
RSVD
Reserved for future use
GT0EN
Counter/timer 0 gate enable:
1 = Gate 0 / DIN 1, CN12 pin 26, acts as an active high gate for counter/timer 0. This pin is connected
to a 10KΩ pull-up resistor.
0 = Counter/timer 0 runs freely with no gating.
SRC0
Counter 0 input source:
1 = Input to Counter 0 is the clock determined by FREQ0 (bit 6).
0 = Input to Counter 0 is CN12 pin 25 (CLK 0 / DIN 0). The falling edge is active. This pin is
connected to a 10KΩ pull-up resistor.
GT12EN
Counter/timer 1/2 and external trigger gate enable:
This bit enables gating for A/D sampling for both internal and external clocking.
1 = When CN12 pin 32 (EXTGATE / DIN 2) is low prior to the start of A/D conversions, A/D
conversions will not begin until it is brought high (trigger mode).
If the pin is brought low while conversions are occurring, conversions will pause until it is brought
high (gate mode). CN12 pin 32 is connected to a 10KΩ pull-up resistor.
0 = The interrupt operation begins immediately once it is set up and the selected clock source begins,
with no external triggering or gating.
Diamond Systems Corporation
Poseidon User Manual
Page 64
