FIFO Threshold Read-back (bit 8): Base+5 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
-
-
-
-
-
-
-
FD9
FD9
FIFO threshold (bit 9). (See FIFO Threshold: Base+6, below)
FIFO Threshold: Base+6 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD8-FD1
FIFO threshold (bits 1-8). This is the level at which the board will generate an interrupt request when
the FIFO is enabled (FIFOEN = 1 in Base + 7). Note that the value written is shifted by 1 bit, i.e.
divided by 2. For example, if you want a FIFO threshold of 256 samples, write a 128 to this register.
The interrupt routine must read exactly this number of samples out each time it runs. The last time the
routine runs, it should read whatever is remaining in the FIFO by monitoring the EF bit (Empty Flag)
in the FIFO status register at Base + 7. When the FIFO is empty, EF = 1, and the FIFO returns the
value hex FF on all read operations.
If you are sampling at a slow rate or want to control when the interrupt occurs, you can set the
threshold to a low value. For example, if you are sampling 16 channels at 10Hz and you want an
interrupt each set of samples, you can set the threshold to 16 (write an 8 to this register), so that an
interrupt will occur each 16 samples. Then the interrupt routine should read out 16 samples from the
FIFO, and you get new data as soon as it is available.
For higher sample rates (100KHz or higher) it may be necessary to increase the threshold above 256,
to around 350 or even 512 with enhanced features enabled. If you set the threshold too high, you may
overrun the FIFO, since the interrupt routine may not respond before the remaining locations are
filled, causing an overflow. An overflow can be detected by checking the OVF bit in the FIFO status
register at Base + 7. The correct threshold for your application can only be determined by testing.
Diamond Systems Corporation
Poseidon User Manual
Page 59
