Diamond Systems Poseidon User Manual Download Page 1

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Poseidon User Manual

EPIC format VIA CPU Board with Integrated Data Acquisition

7463010

v1.

1255 Terra Bella Ave.

Mountain View, CA 94043

Tel (650) 810-2500

Fax (650) 810-2525

www.diamondsystems.com

Diamond Systems Corporation

Poseidon User Manual

Page 1

Summary of Contents for Poseidon

Page 1: ...t VIA CPU Board with Integrated Data Acquisition 7463010 v1 2 Copyright 2007 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com Diamond Systems Corporation Poseidon User Manual Page 1 ...

Page 2: ... Battery Connector 27 LCD Panel LVDS Interface Connector 28 VGA Connector 29 LCD Backlight Connector 30 Power Input Connector 30 USB 2 0 Connectors 31 Serial ATA Connector 32 I O Panel Power 33 Standard JTAG Configuration Interface Factory Use 34 Reference Voltage Test Point Factory Use 34 Board Configuration 35 Power Configuration Options 35 PCI VI O Voltage Setting JP1 35 DAQ Configuration JP2 3...

Page 3: ... and Resolution 77 Overview 77 Unipolar and Bipolar Inputs 77 Input Ranges and Resolutions 77 A D Conversion Formulas 78 Performing an A D Conversion 80 Select the Input Channel 80 Select the Input Range 81 Wait for Analog Input Circuit to Settle 81 Perform an A D Conversion on the Current Channel 81 Wait for the Conversion to Finish 81 Read the Data from the Board 81 Convert the numerical data to...

Page 4: ...ground 92 Performing Auto calibration with Software 93 Performing Auto calibration with dsPIC 93 Digital I O Operation 94 Main Digital I O Internal 82C55 Circuit 94 Auxiliary Digital I O 95 Counter Timer Operation 97 Counter Timer Features and Configuration Options 97 Counter Timer Configuration 97 Counter Timer Access and Programming 97 Watchdog Timer Programming 98 FlashDisk Module 100 Installin...

Page 5: ...oseidon Board Layout 13 Figure 3 CN6 and CN7 Connectors 15 Figure 4 CN3 Connector 16 Figure 5 CN10 Connector 23 Figure 6 CN8 Connector 27 Figure 7 LCD Panel Connector 28 Figure 8 CN4 Connector 30 Figure 9 CN9 Connector 30 Figure 10 Serial ATA Connector 32 Figure 11 Jumper Block JP1 35 Figure 12 JP1 Settings 36 Figure 13 Base Address Configuration Example 37 Figure 14 DMA Channel Selection 37 Figur...

Page 6: ...n to Reset to Zero Scale Example 41 Figure 21 JP6 Jumper 41 Figure 22 ATX Configuration Using JP7 42 Figure 23 RS 422 RS 485 Termination Configuration Options 43 Figure 24 DIO Pull up Pull down Configuration 43 Figure 25 Data Acquisition Block Diagram 50 Figure 26 FlashDisk Module 100 Figure 27 FlashDisk Programmer Board Layout 102 Diamond Systems Corporation Poseidon User Manual Page 6 ...

Page 7: ...al ports and power supplies Description and Features The Poseidon board is an all in one embedded SBC with the following key system and data acquisition features Processor Section Low power fanless 1 0GHz VIA Eden ULV CPU or high performance 2 0GHz VIA C7 CPU 512MB or 1GB 533MHz DDR2 RAM soldered on board system memory 400MHz front side bus 2MB 16 bit wide integrated flash memory for BIOS and user...

Page 8: ...nter timer for user counting and timing functions Programmable gate and count enable Internal and external clocking capability System Features Plug and play BIOS with IDE auto detection 32 bit IDE access and LBA support User selectable COM1 or COM2 terminal mode On board lithium backup battery for real time clock and CMOS RAM ATX power switching capability Programmable watchdog timer I O panel boa...

Page 9: ...Block Diagram Figure 1 shows the Poseidon functional blocks Diamond Systems Corporation Poseidon User Manual Page 9 Figure 1 Poseidon Functional Block Diagram ...

Page 10: ...s featuring dedicated 128 bit data paths for pixel data flow and texture command access An integrated MPEG 2 decoder Dual independent display with separate frame buffers for CRT and flat panel displays Audio The design provides AC97 audio support derived from the South Bridge chip The Via VT1612A CODEC provides audio processing Give special attention to design and routing to minimize noise on the ...

Page 11: ...jumper enabled on these two ports Console redirection feature is incorporated This feature enables keyboard input and character video output to be routed to one of the serial ports The board contains provision for mounting a solid state IDE flashdisk module with capacities ranging from 32MB and greater The module mounts onto the board using a 44 pin 2mm pitch header and a hold down mounting hole w...

Page 12: ...he battery life is greater than four years A connector and jumper are provided to disable the on board battery and enable the use of an external battery instead Watchdog Timer A watchdog timer WDT circuit consists of a programmable timer Diamond Systems Corporation Poseidon User Manual Page 12 ...

Page 13: ...Description Board Layout Figure 2 shows the Poseidon board layout including connectors jumper blocks and mounting holes Diamond Systems Corporation Poseidon User Manual Page 13 Figure 2 Poseidon Board Layout ...

Page 14: ...CN14 I O panel power Standard 2x10 2mm header CN15 Audio I O Standard 2x5 2mm header CN16 VGA Standard 2x5 2mm header CN17 Ethernet Standard 2x5 2mm header CN18 Standard button LED utility connector Standard 2x4 2mm header CN19 PS 2 Mouse and keyboard Standard 2x4 2mm header CN20 RS 232 RS 485 RS 422 serial I O COM1 4 Standard 2x20 2mm header CN21 USB 0 1 USB 2 3 USB 2 0 Standard 2x10 2mm header J...

Page 15: ... SD0 A9 B9 12V LA17 D8 D8 DACK0 IOCHRDY A10 B10 keyed MEMR D9 D9 DRQ0 AEN A11 B11 SMEMW MEMW D10 D10 DACK5 SA19 A12 B12 SMEMR SD8 D11 D11 DRQ5 SA18 A13 B13 IOW SD9 D12 D12 DACK6 SA17 A14 B14 IOR SD10 D13 D13 DRQ6 SA16 A15 B15 DACK3 SD11 D14 D14 DACK7 SA15 A16 B16 DRQ3 SD12 D15 D15 DRQ7 SA14 A17 B17 DACK1 SD13 D16 D16 5 SA13 A18 B18 DRQ1 SD14 D17 D17 MASTER SA12 A19 B19 REFRESH SD15 D18 D18 GND SA1...

Page 16: ... C BE1 AD15 3 3V 9 SERR GND Reserved PAR 10 GND PERR 3 3V Reserved 11 STOP 3 3V LOCK GND 12 3 3V TRDY GND DESEL 13 FRAME GND IRDY 3 3V 14 GND AD16 3 3V C BE2 15 AD18 3 3V AD17 GND 16 AD21 AD20 GND AD19 17 3 3V AD23 AD22 3 3V 18 IDSEL0 GND IDSEL1 IDSEL2 19 AD24 C BE3 VI O IDSEL3 20 GND AD26 AD25 GND 21 AD29 5V AD28 AD27 22 5V AD30 GND AD31 23 REQ0 GND REQ1 VI O 24 GND REQ2 5V GNT0 25 GNT1 VI O GNT2...

Page 17: ...yboard data keyboard PS 2 pin 1 Mouse data mouse PS 2 pin 1 Keyboard clock keyboard PS 2 pin 5 Mouse clock mouse PS 2 pin 5 Ground PS 2 pin 3 Utility Connector Connector CN18 is a 2 4 pin header for access to the standard button LED connections Speaker 1 2 PW LED ATX power button 3 4 Ground 5 6 Ground Reset key 7 8 The following table describes the CN18 connector pinouts Diamond Systems Corporatio...

Page 18: ...or this function Under Windows and some other OSs this power down event may cause the system to shut down Typically this is software configurable via an option setting for the given OS If the system is currently powered up and active holding this button for four seconds causes a forced system shutdown This is a hardware power down which can be detrimental to many OSs due to the fact that they are ...

Page 19: ...0 Digital I O port B programmable direction DIO C7 C0 Digital I O port C programmable direction DIN0 1 Digital input port with counter timer and external trigger functions DOUT0 2 Digital output port with counter timer functions CLK0 Input source to Ctr 0 GATE0 Pin to control gating of Ctr 0 CROUT0 Counter 0 output CROUT2 Counter 2 output AD_RCB A D convert signal output can be used to synchronize...

Page 20: ...t 2 Vout 1 35 36 Vout 2 Vout 3 37 38 Analog ground Vout 3 37 38 Analog ground DIN3 EXTCLK 39 40 Digital ground DIN3 EXTCLK 39 40 Digital ground Signal Definition Vout3 0 Analog output channels 3 0 Analog Ground 0V analog reference Vin 31 Vin 0 Analog input channels 31 0 in single ended mode Vin 15 Vin 0 High side of input channels 15 0 in differential mode Vin 15 Vin 0 Low side of input channels 1...

Page 21: ...wer reference 9 10 Audio ground Signal Definition Headphone Line Out Line Level output capable of driving headphones which is referred to as Headphone Out in most sound documentation Line Input Line Level input which is referred to as Line In in most sound documentation Microphone Input Microphone level mono input phantom power provided via pin 9 Power reference Microphone power reference Audio gr...

Page 22: ... MID line which may be tied to the center tap of a potentiometer with HIGH on one side and LOW on the other to give a full range of power control Shorting MID to LOW mutes the speaker audio Shorting MID to HIGH provides maximum gain Default no connection provides 10dB of gain The maximum output power is specified to provide up to two Watts into a 4 Ohm speaker load Note that this output power is d...

Page 23: ... switched 2 Ground 3 Ground 4 12v switched Signal Definition 5v This is provided by the on board power supply derived from the input power It is switched off when the board is powered down 12v This is provided by the 12V input pin on the main power connector It is switched off when the board is powered down Ground These are 0V ground references for the power output voltage rails above Cable no 698...

Page 24: ...2 13 14 D13 D1 15 16 D14 D0 17 18 D15 Ground 19 20 Key not used DRQ 21 22 Ground IDEIOW 23 24 Ground IDEIOR 25 26 Ground IORDY 27 28 Ground DACK 29 30 Ground IRQ15 31 32 Pulled low for 16 bit operation A1 33 34 Not used A0 35 36 A2 CS1 37 38 CS3 LED 39 40 Ground 5v 41 42 5v Ground 43 44 Not used Diamond Systems Corporation Poseidon User Manual Page 24 ...

Page 25: ...s 1 10 PORT2 Pins 11 20 PORT3 Pins 21 30 PORT4 Pins 31 40 The following tables list the signals for each mode of operation including the DE 9 pin numbers associated with the signals RS 232 Pin Assignment COM1 DCD1 1 2 DSR1 RXD1 3 4 RTS1 TXD1 5 6 CTS1 DTR1 7 8 RI1 GND 9 10 N C COM2 DCD2 11 12 DSR2 RXD2 13 14 RTS2 TXD2 15 16 CTS2 DTR2 17 18 RI2 GND 19 20 COM3 DCD3 21 22 DSR3 RXD3 23 24 RTS3 TXD3 25 ...

Page 26: ...d RS 485 Pin Assignment Only CN20 connector pins 21 through 40 PORT3 and PORT4 are used for RS 485 COM3 NC 21 22 NC TXD RXD 3 23 24 TXD RXD 3 GND 25 26 NC NC 27 28 NC GND 29 30 NC COM4 NC 31 32 NC TXD RXD 4 33 34 TXD RXD 4 GND 35 36 NC NC 37 38 NC GND 39 40 NC Signal Definition DE 9 Pin Direction TXD RXD n Differential Transceiver Data HIGH pin 2 bi directional TXD RXD n Differential Transceiver D...

Page 27: ... an external battery The battery voltage for this input should be 3 3 5V The current draw averages under 4µA at 3V 1 Battery input 2 Ground In addition to the external battery connected to CN8 the on board battery and an additional external battery input on Utility Connector CN18 are other possible sources for maintaining the Real Time Clock and the CMOS settings BIOS settings for various system c...

Page 28: ...D2 clock LCD1 clock 21 22 LCD2 clock Ground 23 24 Ground LCD1 data 3 25 26 LCD2 data 3 LCD1 data 3 27 28 LCD2 data 3 VDD LCD display 29 30 VDD LCD display Signal Definition LCD1 Data 3 0 Primary Data Channel bits 3 0 LVDS Differential signaling LCD1 Clock Primary Data Channel Clock LVDS Differential signaling LCD2 Data 3 0 Secondary Data Channel bits 3 0 LVDS Differential signaling LCD2 Clock Seco...

Page 29: ...nal positive 0 7Vpp into 75 Ohm load G Ground Ground return for GREEN signal Blue BLUE signal positive 0 7Vpp into 75 Ohm load B Ground Ground return for BLUE signal DDCclock data Digital serial I O signals used for monitor detection DDC1 specification HSYNC Horizontal sync VSYNC Vertical sync Note While the DDC serial detection pins are present a 5V power supply is not provided the old Monitor ID...

Page 30: ...und Ground for LCD Backlight assembly The control signal is used to allow the system to power down the backlight when the system enables monitor power down during power management control The 12V supply is removed when the system is powered down Power Input Connector The standard Poseidon input power is supplied through the CN9 connector from an external mid range supply PS_ON 1 5 5V standby Groun...

Page 31: ...ge inputs In particular many disk drives need extra current during startup If your system fails to boot properly or if disk accesses do not work correctly the first thing to check is the power supply voltage level Many boot up problems are caused simply by insufficient voltage due to excess current draw on the Vin supply during initialization Multiple 5V and ground pins are provided for extra curr...

Page 32: ...USB ports 0 3 Serial ATA Connector Connector CN5 is the serial ATA connector 1 Ground 2 TX 3 TX 4 Ground 5 RX 6 RX 7 Ground 8 Ground 9 Ground Signal Definition TX TX Differential outputs to PHY RX RX Differential inputs from PHY Ground Ground Diamond Systems Corporation Poseidon User Manual Page 32 Figure 10 Serial ATA Connector ...

Page 33: ...in 17 18 12V in 5V standby 19 20 PS_ON Signal Definition 5V in 5V input 12V in 12V input 5V standby 5V standby power powers board when in standby mode PS_ON Power Supply ON Feedback pin for external ATX supply when needed pulled low when on board power is inactive Ground Ground Note Optionally a PC 104 power supply may be used to power the board through the PC 104 bus Diamond Systems Corporation P...

Page 34: ...MS Signal Definition 3 3V Power GND Ground CTCK Test clock input FTDO Test data output CTDI Test data input CTMS Test mode select Reference Voltage Test Point Factory Use Connector J2 is the reference voltage test point for use during factory calibration 1 Vref 2 GND Signal Definition Vref Reference voltage GND Ground Diamond Systems Corporation Poseidon User Manual Page 34 ...

Page 35: ...le summarizes the configuration for each option JP7 refers to the ATX jumper on Poseidon while JP1 refers to the external power enable jumper on the panel board To locate this jumper see the PNL PSD panel board description in the final section of this manual The table indicates the pin numbers where one jumper must be installed When powering the board using PS 5V 04 via the MOLEX connector and BOO...

Page 36: ...rds plugged into the system PC 104 Plus cards should be keyed to identify the correct voltage setting No key means that the card is universal and can accept either power setting There are essentially 4 possibilities Card keyed for 5V Card keyed for 3 3V Card not keyed universal can operate with either voltage setting Card incorrectly keyed or not keyed but with certain requirements The first three...

Page 37: ...ction is not used for standard PC 104 cards only the PCI signaling of PC 104 Plus Figure 12 shows how to select the desired voltage using jumper JP1 Diamond Systems Corporation Poseidon User Manual Page 37 Figure 12 JP1 Settings ...

Page 38: ... the possible jumper configurations using pins 9 14 and corresponding base addresses Base Address 9 10 11 12 13 14 140h In In In 340h In In Out 100h In Out In 180h In Out Out 200h Out In In 280h Out In Out 300h default Out Out In 380h Out Out Out For example Figure 13 shows the pin configuration for base address 100h DMA Level Selection Jumper block JP2 contains pins for selecting the DMA level Se...

Page 39: ...e A D data To do this jumper pins 15 and 16 on JP2 A 16 bit transfer only occurs during a 16 bit read instruction from the base address A D data when the jumper is installed Otherwise the A D board and host CPU ignore the 16 bit setting and or instruction and convert the 16 bit operation into two 8 bit read operations Jumper pins 15 and 16 as shown in Figure 15 below to select 16 bit operation COM...

Page 40: ...ion offers two advantages It allows for greater noise immunity because the noise which is present in equal amounts and equal phase on both the high and low inputs is subtracted out when the low input is subtracted from the high input It allows for the signal to float away from ground Normally the ground of the signal source is still connected to the ground on the A D board in order to keep the sig...

Page 41: ...niversal Driver software to set programmable D A range because it requires calibration to fine tune the setting to the desired value To configure the analog output range set jumper block JP5 according to the tables below The first four positions are used for the output range and the fifth position is for the power up reset mode Output Range 10V 5V Programmable Polarity D A Clear Select 5V Out In O...

Page 42: ... Figure 20 shows the jumper setting to configure the DACs to reset to zero scale Omit the jumper to reset to mid scale Battery Connection JP6 The CMOS RAM may be cleared using the 3 pin JP6 jumper block By default there are jumpers on pins one and two for standard BIOS configuration Diamond Systems Corporation Poseidon User Manual Page 42 Figure 19 D A Configuration for 5V Output Range Example Fig...

Page 43: ...or If the ATX jumper is out ATX works normally and an external momentary switch may be used to turn power ON and OFF A quick contact turns the power ON and a long contact greater than four seconds turns the power OFF If the ATX jumper is in the ATX function is bypassed and the system powers up as soon as power is connected If the ATX jumper is removed the battery backup for CMOS and the real time ...

Page 44: ...shows the termination configuration options The default configuration is no termination DIO Pull up Pull down Configuration JP9 Configure the DIO lines for pull up or pull down using jumper block JP8 as shown in Figure 22 By default the lines will be pulled high Diamond Systems Corporation Poseidon User Manual Page 44 Figure 23 RS 422 RS 485 Termination Configuration Options Figure 24 DIO Pull up ...

Page 45: ...gured in the BIOS Console Redirection to a Serial Port In many applications without a local display and keyboard it may be necessary to obtain keyboard and monitor access to the CPU for configuration file transfer or other operations Poseidon supports this operation by enabling keyboard input and character output onto a serial port referred to as console redirection A serial port on another PC can...

Page 46: ... as follows 1 For Console Type select PC ANSI 2 You can modify the baud rate and flow control here if desired 3 At the bottom for Continue C R after POST select Off default to turn off after POST or select On to remain on always 4 Exit the BIOS and save your settings Flash Memory Poseidon contains a 2Mbyte 16 bit wide flash memory chip for storage of BIOS and other system configuration data Backup...

Page 47: ... ISA Reset signal is an active high pulse with a 200ms duration The PCI Reset is active low with a typical pulse width duration of 200 msec On Board Video Using the the on board VIA CX700 processor Poseidon integrates all of the support needed for modern media Refer to the VIA Technologies Inc documentation for CX700 series processors listed in the Additional Information section of this document D...

Page 48: ...ration to modify the base address and interrupt level The settings of COM3 and COM4 I O addresses may be changed using jumpers J5 The jumper settings are auto detected by the BIOS Note The IRQ settings for COM3 and COM4 are selected using jumper J4 COM3 may use IRQ4 IRQ7 or IRQ10 COM4 may use IRQ3 IRQ7 or IRQ10 Once these jumper selections are made you must update the serial port IRQ settings in t...

Page 49: ... 2 Send data which is echoed to the receive buffer of the same port 3 Set RTS low to disable transmit 4 Verify that data is received and that it matches the transmit data If the data does not match re transmit the data RS 422 Mode COM3 and COM4 are independently selectable to operate in RS 422 mode instead of RS 232 mode default or RS 485 mode Jumper the J4 connector RS 422 pins to override the BI...

Page 50: ...The USB ports can be used for keyboard and mouse at the same time that the PS 2 keyboard and mouse are connected Diamond Systems Corporation Poseidon User Manual Page 50 ...

Page 51: ...uns with no change on Poseidon with the exception that the Poseidon DAQ does not have an equivalent to the DMM 32X AT serial port Poseidon has the following Data Acquisition Circuit features 32 analog inputs with 16 bit A D and 250KHz sample rate 4 analog outputs with 12 bit D A and 100KHz waveform output capability 24 digital I O lines 2 counter timers interrupt and DMA A D transfers using an enh...

Page 52: ...FO Threshold Read back bits 7 0 7 FIFO Control FIFO Status 8 Miscellaneous and Page Control A D Status 9 Interrupt and A D Clock Control Interrupt and A D Clock Status 10 Counter Timer and DIO Control C T and DIO Control Read back 11 Analog Configuration Analog I O Read back Page 0 82C54 Counter Timer Access Base Write Function Read Function 12 Counter 0 Data Counter 0 Data Read back 13 Counter 1 ...

Page 53: ...dsPIC Address dsPIC Address Read back 14 Auto calibration Command Auto calibration Status 15 dsPIC Programming Control dsPIC Programming Status Page 5 D A Waveform Generator Enhanced Feature Page Base Write Function Read Function 12 Waveform Buffer Address LSB 13 Waveform Buffer Address MSB 14 Waveform Generator Control Waveform Generator Control Read back 15 Waveform Generator Command Note Page 6...

Page 54: ...R2D0 15 SC1 SC0 RW1 RW0 M2 M1 M0 BCD Page 1 82C55 Type Digital I O 12 A7 A6 A5 A4 A3 A2 A1 A0 13 B7 B6 B5 B4 B3 B2 B1 B0 14 C7 C6 C5 C4 C3 C2 C1 C0 15 1 MODEC MODEA DIRA DIRCH MODEB DIRB DIRCL Page 2 FIFO Control Enhanced Feature Page 12 FD9 13 14 15 Page 3 Autocalibration Registers 12 D7 D6 D5 D4 D3 D2 D1 D0 13 A6 A5 A4 A3 A2 A1 A0 14 EE_EN EE_RW RUNCAL MUXEN TDACEN 15 EE_ACC Page 4 dsPIC Interfa...

Page 55: ... CTR1D2 CTR1D1 CTR1D0 14 CTR2D7 CTR2D6 CTR2D5 CTR2D4 CTR2D3 CTR2D2 CTR2D1 CTR2D0 15 SC1 SC0 RW1 RW0 M2 M1 M0 BCD Page 1 82C55 Type Digital I O 12 A7 A6 A5 A4 A3 A2 A1 A0 13 B7 B6 B5 B4 B3 B2 B1 B0 14 C7 C6 C5 C4 C3 C2 C1 C0 15 1 MODEC MODEA DIRA DIRCH MODEB DIRB DIRCL Page 2 FIFO Control Enhanced Feature Page 12 FD9 13 14 15 Page 3 Autocalibration Registers 12 D7 D6 D5 D4 D3 D2 D1 D0 13 A6 A5 A4 A...

Page 56: ...t DMA or external trigger mode A D LSB bits 7 0 Base 0 Read Bit 7 6 5 4 3 2 1 0 Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD7 AD0 A D data bits 7 0 AD0 is the LSB Auxiliary Digital Output Base 1 Write Bit 7 6 5 4 3 2 1 0 Name LED DOUT2 DOUT1 DOUT0 LED Toggles the on board user LED 1 on 0 off DOUT2 0 Auxiliary digital output bits on analog I O header CN12 Two pins also serve as optional counter outputs ...

Page 57: ... H0 H4 H0 The high channel number setting in the A D channel scan range Channel numbers range from 0 to 31 in single ended mode DAC LSB Base 4 Write Bit 7 6 5 4 3 2 1 0 Name DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA0 D A data bits 7 0 for the channel currently being accessed This register is a holding register Writing to it does not affect any D A channel until the MSB is written When the MSB is writ...

Page 58: ...nters 1 and 2 when GT12EN 1 Base 10 bit 0 DIN1 CN12 pin 26 Gate for counter 0 when GT0EN 1 Base 10 bit 2 DIN0 CN12 pin 25 Clock for counter 0 when SRC0 1 Base 10 bit1 DAC MSB Channel Base 5 Write Bit 7 6 5 4 3 2 1 0 Name DACH1 DACH0 DASIM DAGEN DA11 DA10 DA9 DA8 DACH1 0 Binary number of the D A channel 3 0 DASIM D A simultaneous update NOTE If enhanced features are disabled this is always 0 for ba...

Page 59: ... hex FF on all read operations If you are sampling at a slow rate or want to control when the interrupt occurs you can set the threshold to a low value For example if you are sampling 16 channels at 10Hz and you want an interrupt each set of samples you can set the threshold to 16 write an 8 to this register so that an interrupt will occur each 16 samples Then the interrupt routine should read out...

Page 60: ...the A D converter FIFORST FIFO reset 1 Reset FIFO after this command is issued EF 1 TF 0 FF 0 0 No function FIFO Status Base 7 Read Bit 7 6 5 4 3 2 1 0 Name EF TF FF OVF FIFOEN SCANEN PAGE1 PAGE0 EF Empty flag 1 FIFO is empty 0 FIFO is not empty TF Threshold flag 1 FIFO is at or beyond threshold if the FIFO threshold is 256 words this flag is set when the FIFO contains at least 256 words of A D da...

Page 61: ...e Device 000 0 8254 001 1 8255 010 2 FIFO Control 011 3 EEPROM TrimDAC 100 4 dsPIC 101 5 D A Waveform Generator 110 6 Factory Use Only 111 7 Not Used Grayed pages 2 4 5 6 and 7 are only accessible when the enhanced features are enabled Note that P2 is an enhanced feature bit Writing to the page bits will not generate a board reset or interrupt reset as long as those bits are kept at 0 in the data ...

Page 62: ... detail on DMA behavior 1 DMA Enabled 0 DMA Disabled CLKEN Enable hardware clock for A D sampling 1 Enable hardware clock for A D source is selected with CLKSEL bit below NOTE When this bit is 1 software triggers are disabled i e writing to Base 0 will not start an A D conversion 0 Disable hardware clocking for A D A D conversions occur with software command only CLKSEL Hardware clock select enabl...

Page 63: ...o INTRST Base 8 1 Digital interrupt request has occurred 0 No interrupt request TINT Timer interrupt status Cleared by writing to INTRST Base 8 1 Timer interrupt request has occurred 0 No interrupt request DMAEN Read back of control register bit defined above P2 Read back of P2 register bit defined at Base 8 write CLKEN Read back of control register bit defined above CLKSEL Read back of control re...

Page 64: ... for future use GT0EN Counter timer 0 gate enable 1 Gate 0 DIN 1 CN12 pin 26 acts as an active high gate for counter timer 0 This pin is connected to a 10KΩ pull up resistor 0 Counter timer 0 runs freely with no gating SRC0 Counter 0 input source 1 Input to Counter 0 is the clock determined by FREQ0 bit 6 0 Input to Counter 0 is CN12 pin 25 CLK 0 DIN 0 The falling edge is active This pin is connec...

Page 65: ... the full scale voltage range at the A D converter and the full scale voltage range at the input to the board The gain should never cause the input signal to exceed the range of the A D because incorrect measurements will result clipping The A D full scale voltage range is defined by the RANGE and ADBU bits above To calculate the optimum gain setting select the highest gain that does not allow the...

Page 66: ...e you change the channel gain or input range on the board The wait time is approximately 10μS 0 The analog input circuit has settled and a new A D conversion may begin RSVD Reserved for future use SCINT1 0 Read back of control bit described above Only available if enhanced features are enabled RANGE Read back of control bit described above ADBU Read back of control bit described above G1 0 Read ba...

Page 67: ... CTR0D0 CRT0D7 0 Counter 0 data Counter 1 Data Base 13 Read Write Bit 7 6 5 4 3 2 1 0 Name CTR1D7 CTR1D6 CTR1D5 CTR1D4 CTR1D3 CTR1D2 CTR1D1 CTR1D0 CRT1D7 0 Counter 1 data Counter 2 Data Base 14 Read Write Bit 7 6 5 4 3 2 1 0 Name CTR2D7 CTR2D6 CTR2D5 CTR2D4 CTR2D3 CTR2D2 CTR2D1 CTR2D0 CRT2D7 0 Counter 2 data 82C54 Control Base 15 Read Write Bit 7 6 5 4 3 2 1 0 Name SC1 SC0 RW1 RW0 M2 M1 M0 BCD SC1...

Page 68: ...C4 C3 C2 C1 C0 C7 C0 Port C data DIO Control Base 15 Read Write Bit 7 6 5 4 3 2 1 0 Name 1 MODEC MODEA DIRA DIRCH MODEB DIRB DIRCL MODEC A Mode configuration bits These must be set to 0 DIRA DIRCH DIRB DIRCL Direction control bits On ports A and B all the bits in each port must be the same direction On port C the upper half C7 C4 can have a different direction than the lower half C3 C0 0 Output 1 ...

Page 69: ...ible when enhanced features are enabled Expanded FIFO Depth Base 12 Read Write Bit 7 6 5 4 3 2 1 0 Name FD9 FD9 This bit is used when setting the FIFO threshold See the documentation for register Base 6 for more information Diamond Systems Corporation Poseidon User Manual Page 69 ...

Page 70: ... A5 A4 A3 A2 A1 A0 A6 A0 EEPROM TrimDAC address The EEPROM recognizes address 0 127 using address bits A6 A0 of this register The TrimDAC only recognizes addresses 0 7 using bits A2 A0 In each case remaining address bits will be ignored Calibration Control Base 14 Write Bit 7 6 5 4 3 2 1 0 Name EE_EN EE_RW RUNCAL MUXEN TDACEN EE_EN EEPROM Enable Writing a 1 to this bit will initiate a transfer to ...

Page 71: ...ps prevent accidental corruption of the EEPROM contents Once the page is set and this value is written you can make unlimited reads and writes to the EEPROM without resending this key as long as you stay on page 3 Writing 0xA6 to this register enables all enhanced features and sets A D FIFO depth to 1024 samples This enhanced feature state remains in effect until explicitly disabled Writing 0xA7 t...

Page 72: ...CA1 PICA0 PICR W Read write control 0 write 1 read PICA4 0 dsPIC internal address Writing a byte with R W 0 causes the dsPIC to write the data contained in the dsPIC Data Register above to the dsPIC internal address indicated by PICA4 0 Writing a byte with R W 1 causes the dsPIC to read the data at dsPIC internal address PICA4 0 and places the received data in the dsPIC Data Register dsPIC Address...

Page 73: ...cal process immediately Note Set the desired bit to a value of 1 to execute the desired command Only one bit can be set to 1 at a time Bits are processed MSB to LSB The first 1 bit determines which command is executed Auto calibration Status Base 14 Read Bit 7 6 5 4 3 2 1 0 Name ACHOLD PICPRST ACERR ACACT PICBSY ACHOLD 1 dsPIC in holdoff mode auto autocal disabled PICPRST 1 dsPIC device present on...

Page 74: ... If PIC_PGD line is in output mode set low PGCW1 Set PIC_PGC line high PGCW0 Set PIC_PGC line low Note This register is used to control the on board dsPIC microcontroller The dsPIC controls the auto autocalibration process and it also provides the communication link between the board and its serial port Only one bit can be set to 1 at a time Bits are processed MSB to LSB The first 1 bit determines...

Page 75: ...ase 12 Write Bit 7 6 5 4 3 2 1 0 Name DACA7 DACA6 DACA5 DACA4 DACA3 DACA2 DACA1 DACA0 DACA7 0 LSB of address to store D A code in D A waveform buffer Waveform Buffer Address MSB Base 13 Write Bit 7 6 5 4 3 2 1 0 Name DACA9 DACA8 DACA9 8 MSB of address to store D A code in D A waveform buffer Diamond Systems Corporation Poseidon User Manual Page 75 ...

Page 76: ...bits combine to choose which trigger source is used to increment the waveform by one frame WGSRC1 WGSRC0 Description 0 0 Manual using WGINC 0 1 Counter 0 output 1 0 Counter 1 2 output 1 1 External trigger CN12 pin 31 Waveform Generator Command Base 15 Write Bit 7 6 5 4 3 2 1 0 Name WGINC WGRST WGPS WGSTRT WGINC Begin or resume the waveform generator WGRST Pause stop the waveform generator The curr...

Page 77: ...able enhanced features 1 Set page bits to Page 3 2 Write code to unlock enhanced features Below is the code demonstrating how to enable enhanced features without using the driver software The page bit can be set using the register at Base 8 outp Base 8 0x3 Write 0xA6 to register Base 15 to unlock enhanced features outp Base 15 0xA6 Normal Mode To disable enhanced features follow the same instructi...

Page 78: ...gain you can that will allow the A D converter to read the full range of voltages over which your input signals will vary If the gain is too high the A D converter will clip at either the high end or low end and you will not be able to read the full range of voltages on your input signals Input Ranges and Resolutions The table below lists the full scale input range for each valid analog input conf...

Page 79: ...lar ranges and one for unipolar ranges To convert the A D value to the corresponding input voltage use the following formulas Conversion Formula for Bipolar Input Ranges Input voltage A D code 32768 Full scale input range Example Given Input range is 5V and A D code is 17761 Therefore Input voltage 17761 32768 5V 2 710V For a bipolar input range 1 LSB 1 32768 Full scale voltage The table below sho...

Page 80: ...ange 1 LSB 1 65536 Full scale voltage The following table illustrates the relationship between A D code and input voltage for a unipolar input range VFS Full scale input voltage A D Code Input Voltage Symbolic Formula Input Voltage for 0 10V Range 32768 0V 0 0000V 32767 1 LSB VFS 65536 0 153mV 1 VFS 2 1 LSB 4 99985V 0 VFS 2 5 0000V 1 VFS 2 1 LSB 5 00015V 32767 VFS 1 LSB 9 9998V Diamond Systems Cor...

Page 81: ...e FIFO and clears SCANEN and FIFOEN outp Base 7 0x0A resets the FIFO and SCANEN but leaves FIFOEN set Note that this register also contains a FIFO enable bit FIFOEN This bit only has meaning during A D interrupt operations The FIFO is always enabled and is always in use during A D conversions Perform an A D conversion according to the following steps Each step is discussed in detail below 1 Select...

Page 82: ...ettling and when it is safe to sample the input When WAIT is 1 the board is settling When WAIT is 0 the board is ready for an A D conversion Perform an A D Conversion on the Current Channel To generate an A D conversion simply write to Base 0 to start the conversion Any value may be written to the register Wait for the Conversion to Finish The A D converter takes about four microseconds to complet...

Page 83: ...of the FIFO Therefore you can read each A D sample as soon as it is ready or you can wait until you take a collection of samples up to 1024 maximum and then read them all out in sequence Convert the numerical data to a meaningful value Once you have the A D value you need to convert it to a meaningful value The A D conversion formulas describe how to convert the A D data back to the original input...

Page 84: ...le the time between scans depends on the software or external trigger and may be very short or very long but is usually less than about 100Hz above this rate use interrupt scans below No No Yes Interrupt Single Conversion Low Speed Used for controlled rate sampling of single channels or multiple channels in round robin fashion where the frequency of sampling must be precise but is relatively slow ...

Page 85: ...f samples is not an integral number of scans For example if you have a scan size of 10 and a FIFO threshold of 256 the first time the interrupt routine runs it reads 256 samples consisting of 25 full scans of all 10 channels followed by 6 samples from the next scan The next time the interrupt routine runs it reads the next 256 samples consisting of the remaining 4 samples from the last scan it sta...

Page 86: ...he on board 32 bit counter timer is programmed to the desired sample rate For external clocking the signal EXTCLK DIN3on I O header CN13 pin 39 controls sampling Falling edges on this pin generate A D conversions The signal is edge sensitive holding it low generate one conversion 4 A D conversion rate if using internal clock If internal clocking is selected provide the desired sample rate in Hz as...

Page 87: ...ge For a 12 bit DAC the resolution is 1 212 or 1 4096 of the full scale output range This smallest change results from an increase or decrease of 1 in the D A code so this change is referred to as 1 least significant bit 1 LSB The value of this LSB is calculated as follows 1 LSB Output voltage range 4096 The maximum voltage swing is defined as the difference between the highest nominal output volt...

Page 88: ...nerate the actual full scale reference voltage which would require an output code of 4096 that is not possible with a 12 bit number The maximum output value is 4095 Therefore the maximum possible output voltage is 1 LSB less than the full scale reference voltage Unipolar Mode D A Formula Output value Output voltage Full scale voltage 4096 Example Desired output voltage 2 168V full scale voltage 5V...

Page 89: ... MSB to the Board The LSB is written to Base 4 and the MSB channel no is written to Base 5 If you are using enhanced features be sure to enable enhanced features before writing to the registers Monitor the DACBUSY Status Bit DACBUSY 1 for 10µS while the data in registers Base 4 and Base 5 are serially shifted into the D A chip After DACBUSY returns to 0 you can write to register Base 4 and Base 5 ...

Page 90: ...ng DASIM 1 To update MSB MSB 0xDF To latch MSB MSB 32 5 Write LSB and MSB to board enable enhanced features if using latching outp Base 8 3 select page 3 outp Base 15 0xA6 enable enhanced features outp Base 4 LSB outp Base 5 MSB 6 Monitor DACBUSY bit Base 4 bit 7 while inp Base 4 0x80 Diamond Systems Corporation Poseidon User Manual Page 90 ...

Page 91: ...t counters 1 2 output external trigger The memory block also allows a programmable depth which when hit will wrap and return to the beginning The threshold ranges from 64 to 1024 and is programmable in multiples of 64 Programming the D A Waveform Generator This section details how to program the D A waveform generator through direct I O without using the Diamond Systems driver software Please note...

Page 92: ...d counter 1 2 is used for A D interrupts Counter 1 2 should be used when a consistent rate is desired and counter 0 is used for other interrupt functions or if you want to synchronize the waveform generator to A D interrupt functionality External trigger should be used when an external signal is desired to generate D A waveform Input source is set on Page 5 Base 14 bits 0 and 1 The number of the c...

Page 93: ...d their values are stored in the on board EEPROM for use by the calibration program Note that the actual values of the reference signals does not matter as long as they are stable since the calibration routine knows the values and can adjust the calibration circuit to achieve them An extra input multiplexor chip is used to feed the calibration voltages into the A D circuit during the process For b...

Page 94: ...to auto calibration is enabled by writing a 1 to Page 4 Base 14 bit 3 ACREL When this bit is set the Autocal holdoff line is released The dsPIC monitors temperature changes and auto calibrates the board every 5ºC If more control over auto auto calibration is desired set the ACHOLD bit to stop the temperature trigger this is the default state and use the ACTRIG bit to engage auto calibration when d...

Page 95: ... bit in this register will not change the contents of the page bits The current page may be determined by reading the page bits at Base 7 This digital I O circuit functions like an 82C55 in Mode 0 direct I O or Mode 1 latched I O In Mode 1 latch and acknowledge signals are provided Each port A B and C can be programmed for input or output Port C can also be split into two halves with each half pro...

Page 96: ...that can be used either for general purpose digital I O or for A D and counter timer functions The operation of these bits is controlled with various bits in two control registers Outputs DOUT2 CTROUT2 CN12 pin 28 The function of this pin is determined by OUT2EN Base 10 bit 5 DOUT1 SHOUT CN12 pin 30 This pin is always the value written to DOUT1 at Base 1 bit 1 DOUT0 CTROUT0 CN12 pin 27 The functio...

Page 97: ...l may always be read at Base 4 bit 0 It may function as an external clock for counter 0 when SRC0 0 in Base 10 bit 1 When used as a clock for Counter 0 the rising edge is active Diamond Systems Corporation Poseidon User Manual Page 97 ...

Page 98: ...ng control Counter Timer Configuration The counter timer configuration is determined by the control register at Base 10 Note that the outputs of counters 0 and 2 are routed to pins on I O header CN12 under software control rather than being hardwired Configuring the A D sampling clock is done with the control register at Base 9 Bit CLKEN selects whether or not the A D hardware clocking is enabled ...

Page 99: ...Read back 7 25Fh Watchdog Enable Watchdog Status Watchdog Trigger Base 4 Write Bit 7 6 5 4 3 2 1 0 Name WDTRIG WDTRIG Writing a one to this bit triggers the watchdog timer Watchdog Configuration Base 5 Read Write Bit 7 6 5 4 3 2 1 0 Name WDT3 WDT2 WDT1 WDT0 WDT3 0 Watchdog timer reload value Each internal clock tick decrements the watchdog counter by one from this value A tick interval is 0 2 seco...

Page 100: ...0 in Base 5 and starts the internal counter 2 When the watchdog is enabled and the internal counter is running keep the watchdog from expiring by setting the WDTRIG bit in Base 4 This reloads the counter with the value in Base 5 If the counter reaches zero watchdog circuitry pulses the reset line and disables the watchdog timer 3 Disable the watchdog timer at any time by writing any value other th...

Page 101: ...rt Model Capacity FD 128 XT 128MB FD 256 XT 256MB FD 512 XT 512MB FD 1G XT 1GB FD 2G XT 2GB FD 4G XT 4GB Installing the FlashDisk Module The FlashDisk module installs directly on the IDE connector CN2 and is held down with a spacer and two screws onto a mounting hole on the board For master mode install the jumper on pins 3 and 4 For slave mode install the jumper on pins 1 and 2 Diamond Systems Co...

Page 102: ... cable carries power from the CPU to the adapter board and powers the FlashDisk module and any drive using a 44 pin connector such as a notebook hard drive A drive utilizing a 40 pin connector such as a CD ROM or full size hard drive requires an external power source through an additional cable The power may be provided from the CPU s power out connector J12 or from one of the two 4 pin headers on...

Page 103: ...r CD ROM drive A dedicated connector J2 is provided for the FlashDisk module Any two devices may be connected simultaneously using this board with proper master slave jumper configurations on the devices The FlashDisk Programmer Board comes with a 44 wire cable no DSC no 6981004 and a 40 wire cable no DSC no C 40 18 for connection to external drives The FlashDisk module is sold separately The 44 p...

Page 104: ...2mm 12 6981073 Digital I O IDC34 to IDC34 2mm 12 6981080 Ethernet 1G 2mm to panel 6981081 Serial 2mm to 2x DB9M 6981082 USB 2mm to 2x USB 6981083 PS2 2mm to 2x Mini DIN 6981084 VGA 2mm to DD15F 6981085 Audio 2mm to 3x 3 5mm 6981087 Poseidon Speaker Out 6981088 Poseidon Utilities 6981091 Poseidon Power In Diamond Systems Corporation Poseidon User Manual Page 104 ...

Page 105: ...he system boot sequence will be impeded by these conflicts Take care to read through this documentation particularly the section on ISA Resource defaults to familiarize yourself with the internal resources used before adding components that might cause conflicts When adding boards to the PC 104 board stack be sure to include board standoffs Inordinate flexing of the main PC 104 and PC 104 Plus con...

Page 106: ...ins 2 3 Please consult the Poseidon power configuration table on page 35 for complete information on all the different power options n Shutdown Disable JP2 Install a jumper in positions 1 2 of JP2 to disable the shutdown output control If the panel board and SBC are to be used with a Jupiter JMM power supply with shutdown control remove the jumper or install a jumper between pins 2 3 2 I O Connect...

Page 107: ...lity Header The 2x4 Poseidon utility header should be mirrored on the topside using a 2x4 2mm SMT male pin header 2 5 User I O Connectors All user I O connectors are mounted on the top side of the board and are accessed through openings in the front panel of the enclosure All I O connectors provide a firm latching method wherever possible All connectors should be aligned such that their faces are ...

Page 108: ... in line out use standard jack colors Power DB9 female 2 6 Reset Switch The reset switch is a momentary switch that is accessible only through a small hole that can accommodate a paper clip 2 7 DC DC Power I O The Panel board will interface with an internal DC DC converted using two connectors A 1x6 0 156 straight friction lock header will carry the variable power input ref Molex 26 48 1065 1 Vari...

Page 109: ...Shut Down Circuit This circuit is required to make the panel compatible with our Jupiter series power supply PS_SHUT_DOWN Connect to PS Shut Down on internal headers POWER_INPUT Connect to Variable Power Input line POWER_SWITCH Connect to pin 3 of the Poseidon utility header REMOTE_ON_OFF Connect to pin 20 of the Poseidon power header Diamond Systems Corporation Poseidon User Manual Page 109 ...

Page 110: ...t is industry standard DTE while the RS 422 485 pinouts are DSC standard Pin RS 232 RS 422 ports 3 4 only RS 485 ports 3 4 only 1 DCD NC NC 2 RXD TXD TX RX 3 TXD Ground Ground 4 DTR RXD NC 5 Ground Ground Ground 6 DSR NC NC 7 RTS TXD Tx RX 8 CTS RXD NC 9 RI NC NC 3 4 USB The 4 USB connectors use the industry standard pinout The connector shield is connected to the shield pins of the CPU connectors...

Page 111: ...11 NC 12 SDA 13 Hsync 14 Vsync 15 SCL 3 6 Power Input The input power connector is a DB9 female connector with connections for 5VDC input and also a variable DC voltage input Only one of these inputs is used at a time 12V may also be provided via this connector for use by an LCD backlight 1 5V 2 5V 3 Gnd 4 Vin 5 12V 6 5V 7 Gnd 8 Gnd 9 Vin Diamond Systems Corporation Poseidon User Manual Page 111 ...

Page 112: ...rnal headers It will extend no further than required to support the connectors along the lower edge of the Poseidon The panel must not interfere with the speaker digital I O or analog I O headers on the Poseidon board Side view artist s rendering Overhead view 4 2 Mounting Hardware The panel board ships with a hardware kit consisting of two male female spacers with 4 40 threads and two 4 40 x 1 4 ...

Page 113: ...st of the board I O connections Connectors with extra gold contact plating Alternative heatsinks for low air flow and dusty environments Conformal Coating Jumperless configuration all settings made on board with no jumper headers required Contact your sales representative for details on these special order options Diamond Systems Corporation Poseidon User Manual Page 113 ...

Page 114: ...anges 0 10V 0 5V 0 2 5V 0 1 25V 0 625V Input bias current 100pA max Protection 35V on any analog input without damage Input Impedance 10 13 ohms Nonlinearity 3LSB no missing codes Conversion rate 250 000 samples sec max On board FIFO 1024 samples programmable threshold A D and D A Calibration Automatic using on board microcontroller and temp sensor Analog Outputs 4 12 bit resolution Output ranges ...

Page 115: ...ower Supply Input Voltage 5VDC 5 General Dimensions 4 528 x 6 496 115mm x 165mm Weight PSDE10 512N 8 3 oz PSDE10 512A 8 6 oz PSDC20 1024A 9 0 oz Diamond Systems Corporation Poseidon User Manual Page 115 ...

Page 116: ...Diamond Systems Corporation http www diamondsystems com 2 VIA Technologies Inc Processors http www via com tw en products processors 3 VIA Technologies Inc North South bridge http www via com tw en products chipsets c series cx700 Diamond Systems Corporation Poseidon User Manual Page 116 ...

Page 117: ... for COM3 3 COM4 select for IRQ 4 COM3 select for IRQ 5 IRQ3 selectable for COM4 or COM3 6 IRQ4 selectable for COM3 or ADC 7 COM3 select for IRQ 8 AD select for IRQ 9 AD select for IRQ 10 IRQ5 selectable for COM3 or ADC 11 IRQ6 selectable for COM3 or ADC 12 COM3 select for IRQ Diamond Systems Corporation Poseidon User Manual Page 117 ...

Page 118: ...Technical Support For technical support please email support diamondsystems com or contact technical support at 1 650 810 2500 Diamond Systems Corporation Poseidon User Manual Page 118 ...

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