Hercules-EBX CPU User Manual V1.02
Page 68
Base + 15
Write
Command Register
Bit
No.
7 6 5 4 3 2 1 0
Name
FIFORST
DARST
CLRT CLRD CLRA
ADSTART
Each bit in this register represents a command. Writing a 1 to any bit executes the command
specified by that bit. Only one bit may be written to at a time.
FIFORST Reset the FIFO; after this command, OVF, FF, and TF = 0, and EF = 1
DARST
Reset the D/A; all D/A channels will reset to zero-scale
CLRT
Clear timer interrupt request
CLRD
Clear digital I/O interrupt request
CLRA
Clear A/D interrupt request
ADSTART Start an A/D conversion; after this command, ADBUSY = 1 until the A/D conversion
is finished
Base + 15
Read
Hardware Configuration and A/D Channel Readback
Bit
No.
7 6 5 4 3 2 1 0
Name CFG1 CFG0
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
CFG1-0
These bits report the logic level of two input pins on the logic chip that can be used to
indicate the board’s hardware configuration. Currently defaults to “11”.
ADCH4-0 Current A/D channel; this is the channel that will be sampled on the next A/D
conversion.
Base + 16
Read/Write
Digital I/O Port A
Bit
No.
7 6 5 4 3 2 1 0
Name
DIOA7 DIOA6 DIOA5 DIOA4 DIOA3 DIOA2 DIOA1 DIOA0
Base + 17
Read/Write
Digital I/O Port B
Bit
No.
7 6 5 4 3 2 1 0
Name
DIOB7 DIOB6 DIOB5 DIOB4 DIOB3 DIOB2 DIOB1 DIOB0