Hercules-EBX CPU User Manual V1.02
Page 106
16.2 Example : Watchdog Timer With Hardware Trigger
Hardware trigger relies on an external pulse to constantly trigger watchdog timer A. If the external
stream of pulses is ever halted, timer A will reach zero and start timer B. Once timer B reaches 0,
the board will reset.
In this example, we will make use of the “T-1” feature of timer A to automatically reset itself unless
a physical connection is broken. The physical connection must be made between WDO and WDI
on the data acquisition header J9.
Since software is not involved in maintaining the timer, we do can set the reset period to a much
smaller value. In this example, the reset pulse will travel across the physical connection every 10
milliseconds.
outp(base + 0, 0x00);
//set page 0
outp(base + 28, 100 & 0xFF);
//set LSB of WD timer A (10 milliseconds)
outp(base + 29, 100 >> 8) & 0xFF);
//set MSB of WD timer A
outp(base + 30, 0xFF);
//set WD timer B to 0.0255 seconds
outp(base + 31, 0x2D);
//set WDEN=1, WDRST=1, WDT-1=1, WDIEN=1
Now when timer A reaches 1, a rising edge will flow from WDO to WDI, resetting the timer back to
100 and lowering WDO. When the connection from WDO to WDI is severed, the rising edge will
never reach WDI and system will reset.