Elektra CPU User Manual V1.00
Page 67
16. ANALOG CIRCUIT CALIBRATION RESOURCES
For a board with the Data Acquisition option, the Elektra Data Acquisition circuitry incorporates
some advanced calibration features to allow the system to calibrate both the A/D and D/A signal
conversion pathways. The registers involved in controlling these calibration features are listed
below:
Register
Bit Name
Register location
Description
ADUOUT Page 2: Base+13
a one sets A/D section to unipolar input mode
CMUXEN Page 1: Base+14: Bit 4
a one enables calibration voltages multiplexer
SEDIFF Page 2: Base+13
a one sets A/D section to single-ended mode
TrimDAC
Data
Page 1 : Base+12
Data Sent to TrimDAC
TrimDAC
Address
Page 1 : Base+13
Address for TrimDAC
TDACEN Page 1 : Base+14: Bit 3
TrimDAC Enable (when “1”) – note that this is
mutually-exclusive with EE_EN control
Table 18: Calibration Control Signal Listing
AUTO CALIBRATION TABLE:
When Register bit CMUXEN=1, the board is in auto calibration mode. When this mode is enabled,
specific calibration voltages will be fed back to analog channel inputs. There are 5 calibration settings
that can be used (named “VCAL0 – 5” below). These feedback voltages are selected based on the
“ADCH0” and “ADCH1” settings (ADCH4-2 are ignored during auto calibration):
CMUXEN SEDIFF ADCH(1/0)
VCAL VOLTAGE
0
Normal Operation
1 0
0 (0/0)
0 5.5mV
1 0
1(0/1)
1 1.24V
1 0
2 (1/0)
2 2.48V
1 0
3 (1/1)
3 4.96V
1 1
4 VOUT0
Table 19: Calibration Multiplexed Signal Control
Notes:
•
VCAL0 is for bipolar A/D offset adjustments
•
VCAL1 is for unipolar offset adjustments
•
VCAL2 is for full scale 0-1.25, 0-2.5, +/-1.25 and +/-2.5 modes
•
VCAL3 is for full scale 0-5, 0-10, +/-5 and +/-10 modes
•
VCAL4 is D/A VOUT0 for D/A calibration; this loops Analog output “VOUT0” back
