DFI WL968 User Manual Download

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Chapter 1 Introduction

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

AC/HDA_RST#

A30

O CMOS

3.3V Suspend/3.3V

Connect to CODEC pin 11 RESET#

Reset output to CODEC, active low.

AC/HDA_SYNC

A29

O CMOS

3.3V/3.3V

Connect to CODEC pin 10 SYNC

Sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK

A32

I/O CMOS

3.3V/3.3V

Connect to CODEC pin 6 BIT_CLK

Serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT

A33

O CMOS

3.3V/3.3V

Connect to CODEC pin 5 SDATA_OUT

Serial TDM data output to the CODEC.

AC/HDA_SDIN2

B28

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN1

B29

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN0

B30

I/O CMOS

3.3V Suspend/3.3V

Connect 33

Ω

in series to CODEC0 pin 8 SDATA_IN

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A13

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI0+/-

Gigabit Ethernet Controller 0: Media Dependent Interface Differential

Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec

modes. Some pairs are unused in some modes, per the following:

1000BASE-T 100BASE-TX 10BASE-T

MDI[0]+/- B1_DA+/- TX+/-

TX+/-

MDI[1]+/- B1_DB+/- RX+/-

RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

GBE0_MDI0-

A12

I/O Analog

3.3V max Suspend

A10

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI1+/-

GBE0_MDI1-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI2+/-

GBE0_MDI2-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI3+/-

GBE0_MDI3-

I/O Analog

3.3V max Suspend

GBE0_ACT#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK1000#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA0_TX-

A17

O SATA

AC coupled on Module

AC Coupling capacitor

A19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA0_RX-

A20

I SATA

AC coupled on Module

AC Coupling capacitor

B16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA1_TX-

B17

O SATA

AC coupled on Module

AC Coupling capacitor

B19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA1_RX-

B20

I SATA

AC coupled on Module

AC Coupling capacitor

A22

O SATA

AC coupled on Module

SATA2_TX-

A23

O SATA

AC coupled on Module

A25

I SATA

AC coupled on Module

SATA2_RX-

A26

I SATA

AC coupled on Module

B22

O SATA

AC coupled on Module

SATA3_TX-

B23

O SATA

AC coupled on Module

B25

I SATA

AC coupled on Module

SATA3_RX-

B26

I SATA

AC coupled on Module

(S)ATA_ACT#

A28

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Connect to LED and

recommend

current limit resistor 220

Ω

to 3.3V

ATA (parallel and serial) or SAS activity indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A68

AC Coupling capacitor

PCIE_TX0-

A69

AC Coupling capacitor

B68

PCIE_RX0-

B69

A64

AC Coupling capacitor

PCIE_TX1-

A65

AC Coupling capacitor

B64

PCIE_RX1-

B65

A61

AC Coupling capacitor

PCIE_TX2-

A62

AC Coupling capacitor

B61

PCIE_RX2-

B62

A58

AC Coupling capacitor

PCIE_TX3-

A59

AC Coupling capacitor

B58

PCIE_RX3-

B59

A55

AC Coupling capacitor

PCIE_TX4-

A56

AC Coupling capacitor

B55

PCIE_RX4-

B56

A52

AC Coupling capacitor

PCIE_TX5-

A53

AC Coupling capacitor

B52

PCIE_RX5-

B53

D19

AC Coupling capacitor

PCIE_TX6-

D20

AC Coupling capacitor

C19

PCIE_RX6-

C20

D22

C22

PCIE_RX7-

C23

PCIE0_

A88

PCIE0_CLK_REF-

A89

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

D52

PEG_TX0-

D53

C52

PEG_RX0-

C53

D55

PEG_TX1-

D56

C55

PEG_RX1-

C56

D58

PEG_TX2-

D59

C58

PEG_RX2-

C59

D61

PEG_TX3-

D62

C61

PEG_RX3-

C62

D65

PEG_TX4-

D66

C65

PEG_RX4-

C66

D68

PEG_TX5-

D69

C68

PEG_RX5-

C69

D71

PEG_TX6-

D72

C71

PEG_RX6-

C72

D74

PEG_TX7-

D75

C74

PEG_RX7-

C75

D78

PEG_TX8-

D79

C78

PEG_RX8-

C79

D81

PEG_TX9-

D82

C81

PEG_RX9-

C82

D85

PEG_TX10-

D86

C85

PEG_RX10-

C86

D88

PEG_TX11-

D89

C88

PEG_RX11-

C89

D91

PEG_TX12-

D92

C91

PEG_RX12-

C92

D94

PEG_TX13-

D95

C94

PEG_RX13-

C95

D98

PEG_TX14-

D99

C98

PEG_RX14-

C99

D101

PEG_TX15-

D102

C101

PEG_RX15-

C102

PEG_LANE_RV#

D54

I CMOS

3.3V / 3.3V

PU 10K to 3.3V

PCI Express Graphics lane reversal input strap. Pull low on the Carrier

board to reverse lane order.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

DDI/SD

D26

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR0-/SDVO1_RED-

D27

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D29

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR1-/SDVO1_GRN-

D30

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D32

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR2-/SDVO1_BLU-

D33

Connect AC Coupling Capacitors 0.1uF to Device

DDI/S

D36

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR3-/SDVO1_CK-

D37

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

C25

DDI1_PAIR4-/SDVO1_INT-

C26

DDI/SDVO1_

C29

DDI1_PAIR5-/SDVO1_TVCLKIN-

C30

DDI/SDVO1_F

C15

DDI1_PAIR6-/SDVO1_FLDSTALL-

C16

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI1_HPD

C24

I CMOS

3.3V / 3.3V

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI1_DDC_AUX_SEL

D34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI1_CTRL and DDI1_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

D39

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR0-

D40

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D42

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR1-

D43

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D46

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR2-

D47

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D49

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR3-

D50

Connect AC Coupling Capacitors 0.1uF to Device

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high

DDI2_HPD

D44

I CMOS

3.3V / 3.3V

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI2_DDC_AUX_SEL

C34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI2_CTRL and DDI2_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

C39

DDI3_PAIR0-

C40

DDI

C42

DDI3_PAIR1-

C43

DDI

C46

DDI3_PAIR2-

C47

DDI

C49

DDI3_PAIR3-

C50

I/O PCIE

AC coupled on Module

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

DP AUX- function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high

DDI3_HPD

C44

I CMOS

3.3V / 3.3V

DDI Hot-Plug Detect

DDI3_DDC_AUX_SEL

C38

I CMOS

3.3V / 3.3V

Selects the function of DDI3_CTRL and DDI3_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

USB0+

A46

USB0-

A45

USB1+

B46

USB1-

B45

USB2+

A43

USB2-

A42

USB3+

B43

USB3-

B42

USB4+

A40

USB4-

A39

USB5+

B40

USB5-

B39

USB6+

A37

USB6-

A36

USB7+

B37

USB7-

B36

USB_0_1_OC#

B44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 0 and 1. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_2_3_OC#

A44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 2 and 3. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_4_5_OC#

B38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 4 and 5. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_6_7_OC#

A38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 6 and 7. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

AC Coupling capacitor

USB_SSTX0-

AC Coupling capacitor

USB_SSRX0-

AC Coupling capacitor

USB_SSTX1-

AC Coupling capacitor

USB_SSRX1-

D10

AC Coupling capacitor

USB_SSTX2-

AC Coupling capacitor

C10

USB_SSRX2-

D13

AC Coupling capacitor

USB_SSTX3-

D12

AC Coupling capacitor

C13

USB_SSRX3-

C12

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A71

LVDS_A0-

A72

A73

LVDS_A1-

A74

A75

LVDS_A2-

A76

A78

LVDS_A3-

A79

A81

LVDS_A_CK-

A82

B71

LVDS_B0-

B72

B73

LVDS_B1-

B74

B75

LVDS_B2-

B76

B77

LVDS_B3-

B78

B81

LVDS_B_CK-

B82

LVDS_VDD_EN

A77

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel power circuit

LVDS panel power enable

LVDS_BKLT_EN

B79

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel backlight power circuit.

LVDS panel backlight enable

LVDS_BKLT_CTRL

B83

O CMOS

3.3V / 3.3V

Connect to brightness control of LVDS panel backlight power circuit.

LVDS panel backlight brightness control

LVDS_I2C_CK

A83

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC clock of LVDS panel

I2C clock output for LVDS display use

LVDS_I2C_DAT

A84

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC data of LVDS panel

I2C data line for LVDS display use

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

O CMOS

3.3V / 3.3V

LPC frame indicates the start of an LPC cycle

LPC_DRQ0#

PU 10K to 3.3V

LPC_DRQ1#

PU 10K to 3.3V

LPC_SERIRQ

A50

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

LPC serial interrupt

LPC_CLK

B10

O CMOS

3.3V / 3.3V

LPC clock output - 24MHz nominal

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

SPI_CS#

B97

O CMOS

3.3V Suspend/3.3V

Connect to Carrier Board SPI Device CS# pin

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

SPI_MISO

A92

I CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SO pin

Data in to Module from Carrier SPI

SPI_MOSI

A95

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SI pin

Data out from Module to Carrier SPI

SPI_CLK

A94

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SCK pin

Clock from Module to Carrier SPI

SPI_POWER

A91

3.3V Suspend/3.3V

Power supply for Carrier Board SPI – sourced from Module – nominally

3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.

Carriers shall use less than 100mA of SPI_POWER. SPI_POWER

shall only be used to power SPI devices on the Carrier Board.

BIOS_DIS0#

A34

BIOS_DIS1#

B88

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

VGA_RED

B89

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Red for monitor. Analog output

VGA_GRN

B91

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Green for monitor. Analog output

VGA_BLU

B92

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Blue for monitor. Analog output

VGA_HSYNC

B93

O CMOS

3.3V / 3.3V

Connect to VGA connector with a3.3V Buffer IC to isolate PCH & Display Device

Horizontal sync output to VGA monitor

VGA_VSYNC

B94

O CMOS

3.3V / 3.3V

Connect to VGA connector with a 33V Buffer IC to isolate PCH & Display Device

Vertical sync output to VGA monitor

VGA_I2C_CK

B95

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT

B96

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC data line.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

SER0_TX

A98

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 0 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER0_RX

A99

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 0 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_TX

A101

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 1 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_RX

A102

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 1 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

I2C_CK

B33

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

General purpose I2C port clock output

I2C_DAT

B34

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

General purpose I2C port data I/O line

SPKR

B32

O CMOS

3.3V / 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.

This port provides the PC beep signal and is mostly intended for

debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

Output indicating that a watchdog time-out event has occurred.

FAN_PWMOUT

B101

O OD CMOS

3.3V / 3.3V

Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

FAN_TACHIN

B102

I OD CMOS

3.3V / 3.3V

PU 47K to 3V3

Fan tachometer input for a fan with a two pulse output.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

TPM_PP

A96

I CMOS

3.3V / 3.3V

Default NA, PD 4.7K when stuff TPM chip

Trusted Platform Module (TPM) Physical Presence pin. Active high.

TPM chip has an internal pull down. This signal is used to indicate

Physical Presence to the TPM.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

PU 4.7K to 3V3_SB

A falling edge creates a power button event. Power button events can

be used to bring a system out of S5 soft off and other suspend states,

as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU

NC PU 4.7K to 3V3_SB

Reset button input. Active low request for Module to reset and reboot.

May be falling edge sensitive. For situations when SYS_RESET# is

not able to reestablish control of the system, PWR_OK or a power

cycle may be used.

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Reset output from Module to Carrier Board. Active low. Issued by

Module chipset and may result from a low SYS_RESET# input, a low

PWR_OK input, a VCC_12V power input that falls below the minimum

specification, a watchdog timeout, or may be initiated by the Module

software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

PU 10K to 5V and PD 20K

Power OK from main power supply. A high value indicates that the

power is good. This signal can be used to hold off Module startup to

allow Carrier based FPGAs or other configurable devices time to be

programmed.

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Suspend to RAM state. Active low output. An

inverted copy of SUS_S3# on the Carrier Board may be used to

enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 1K to 3V3_DU

PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU

General purpose wake up signal. May be used to implement wake-up

on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 10K to 3V3_DU

Indicates that external battery is low.

This port provides a battery-low signal to the Module for orderly

transitioning to power saving or power cut-off ACPI modes.

LID#

A103

I OD CMOS

3.3V Suspend/12V

PU 47K to 3V3_DU_EC

LID switch. Low active signal used by the ACPI operating system for a LID switch.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SLEEP#

B103

I OD CMOS

3.3V Suspend/12V

PU 10K to 3V3_DU_EC

Sleep button. Low active signal used by the ACPI operating system to bring the

system to sleep state or to wake it up again.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

THRM#

B35

I CMOS

3.3V / 3.3V

PU 10K to 3V3

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK

B13

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus Alert – active low input can be used to

generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

PU 10K to 3.3V

GPI1

A63

PU 10K to 3.3V

GPI2

A67

PU 10K to 3.3V

GPI3

A85

PU 10K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

VCC_12V

A104~A109

B104~B109

C104~C109

D104~D109

Power

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

VCC_5V_SBY

B84~B87

Power

Standby power input: +5.0V nominal. If VCC5_SBY is used, all

available VCC_5V_SBY pins on the connector(s) shall be used. Only

used for standby and suspend functions. May be left unconnected if

these functions are not used in the system design.

VCC_RTC

A47

Power

Real-time clock circuit-power input. Nom3.0V.

GND

A1, A11, A21, A31,

A41, A51, A57, A60,

A66, A70, A80, A90,

A100, A110, B1,

B11, B21 ,B31, B41,

B51, B60, B70, B80,

B90, B100, B110,

C1, C2, C5, C8, C11,

C14, C21, C31, C41,

C51, C60, C70, C73,

C76, C80, C84, C87,

C90, C93, C96,

C100, C103, C110,

D1, D2, D5, D8,

D11, D14, D21,

D31, D51, D60,

D67, D70, D73,

D76, D80, D84,

D87, D90, D93,

D96, D100, D103,

D110

Power

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier

Board GND plane.

Connect to LPC device

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Default NA(Request by BOM option)

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Pin Types

I Input to the Module

O Output from the Module

I/O Bi-directional input / output signal

OD Open drain output

AC coupled off Module

Serial Digital Video Field Stall input differential pair.

O PCIE

AC coupled off Module

DDI 1 Pair 3 differential pairs/Serial Digital Video B clock output differential pair

I PCIE

AC coupled off Module

Serial Digital Video TVOUT synchronization clock input differential pair.

AC coupled off Module

Selection straps to determine the BIOS boot device.

The Carrier should only float these or pull them low, please refer to

below table for strapping options of BIOS disable signals.

LVDS Channel B differential clock

LPC Signals Descriptions

O PCIE

AC coupled off Module

DDI 3 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 3 differential pairs

DDI 3 Pair 2 differential pairs

O PCIE

DDI 3 Pair 1 differential pairs

DDI3_CTRL

C36

DDI3_CTRLDATA_AUX-

C37

O PCIE

AC coupled off Module

DDI 2 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 3 Pair 3 differential pairs

AC coupled off Module

DDI Signals Descriptions

O PCIE

AC coupled off Module

DDI 1 Pair 0 differential pairs/Serial Digital Video B red output differential pair

I PCIE

3.3V / 3.3V

LPC serial DMA request

SPI Signals Descriptions

O PCIE

AC coupled off Module

DDI 2 Pair 2 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 1 differential pairs

O PCIE

AC coupled off Module

DDI2_CTRL

C32

DDI2_CTRLDATA_AUX-

C33

DDI1_CTRL/SDVO1_CTRLCLK D15

DDI1_CTRLDATA_AUX-

/SDVO1_CTRLDATA

D16

AC coupled off Module

DDI 1 Pair 2 differential pairs/Serial Digital Video B blue output differential pair

O PCIE

AC coupled off Module

DDI 1 Pair 1 differential pairs/Serial Digital Video B green output differential pair

Power and GND Signal Descriptions

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

I/O CMOS

3.3V / 3.3V

I CMOS

3.3V / 3.3V

General purpose input pins.

Pulled high internally on the Module.

Power and System Management Signals Descriptions

GPIO Signals Descriptions

O CMOS

Serial Digital Video B interrupt input differential pair.

General purpose output pins.

Upon a hardware reset, these outputs should be low.

VGA Signals Descriptions

3.3V / 3.3V

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

LPC multiplexed address, command and data bus

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel B differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,

LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential clock

O LVDS

LVDS

Connect to LVDS connector

Serial Interface Signals Descriptions

Miscellaneous Signal Descriptions

I CMOS

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 7

LVDS Signals Descriptions

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,

LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 2

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 1

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 6

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 4

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 3

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 5

USB Signals Descriptions

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 14

PCI Express Graphics receive differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 14

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 15

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 15

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 11

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 11

PCI Express Graphics receive differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 8

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 8

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 6

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 5

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 7

AC coupled on Module

PCI Express Graphics transmit differential pairs 7

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 6

PCI Express Graphics transmit differential pairs 4

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 3

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 2

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 3

PCI Express Graphics receive differential pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

I PCIE

PCI Express Graphics transmit differential pairs 2

PEG Signals Descriptions

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 0

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 1

AC coupled off Module

PCI Express Graphics receive differential pairs 1

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Receive Pairs 7

PCIe CLK Buffer

or slot

Reference clock output for all PCI Express and PCI Express Graphics

lanes.

PCI Express Differential Receive Pairs 6

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 7

PCI Express Differential Transmit Pairs 4

PCI Express Differential Receive Pairs 2

PCI Express Differential Transmit Pairs 6

PCI Express Differential Transmit Pairs 3

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 5

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 5

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

AC coupled on Module

PCI Express Differential Transmit Pairs 1

PCI Express Differential Receive Pairs 1

PCI Express Differential Receive Pairs 3

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 0

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 2

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 0

I PCIE

AC coupled off Module

O PCIE

AC97/HDA Signals Descriptions

Serial TDM data inputs from up to 2 CODECs.

Gigabit Ethernet Signals Descriptions

PCI Express Lanes Signals Descriptions

Serial ATA or SAS Channel 0 transmit differential pair.

Connect to SATA0 Conn RX pin

Serial ATA or SAS Channel 0 receive differential pair.

Connect to SATA1 Conn TX pin

Default NA (Request by BOM option)

Serial ATA or SAS Channel 3 transmit differential pair.

Serial ATA or SAS Channel 3 receive differential pair.

Default NA (Request by BOM option)

Serial ATA or SAS Channel 2 receive differential pair.

Serial ATA or SAS Channel 2 transmit differential pair.

Connect to SATA1 Conn RX pin

Serial ATA or SAS Channel 1 receive differential pair.

SATA Signals Descriptions

Connect to SATA0 Conn TX pin

Serial ATA or SAS Channel 1 transmit differential pair.

Ref

Line

Bios

Entry

SPI

Descriptor

Carrier

SPI_CS#

Chipset

SPI CS0#

Destination

Chipset

SPI CS1#

Destination

BIOS

DIS0#

BIOS

DIS1#

Module

SPI0/SPI1

SPI1

(Default)

SPI0

High

Carrier

Carrier

(Default)

Module

(Default)

Module

Module

(Default)

Module

Carrier FWH

SPI0/SPI1

(Default)

SPI0/SPI1

DDI2 is option function

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

AC/HDA_RST#

A30

O CMOS

3.3V Suspend/3.3V

Connect to CODEC pin 11 RESET#

Reset output to CODEC, active low.

AC/HDA_SYNC

A29

O CMOS

3.3V/3.3V

Connect to CODEC pin 10 SYNC

Sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK

A32

I/O CMOS

3.3V/3.3V

Connect to CODEC pin 6 BIT_CLK

Serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT

A33

O CMOS

3.3V/3.3V

Connect to CODEC pin 5 SDATA_OUT

Serial TDM data output to the CODEC.

AC/HDA_SDIN2

B28

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN1

B29

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN0

B30

I/O CMOS

3.3V Suspend/3.3V

Connect 33

Ω

in series to CODEC0 pin 8 SDATA_IN

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A13

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI0+/-

Gigabit Ethernet Controller 0: Media Dependent Interface Differential

Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec

modes. Some pairs are unused in some modes, per the following:

1000BASE-T 100BASE-TX 10BASE-T

MDI[0]+/- B1_DA+/- TX+/-

TX+/-

MDI[1]+/- B1_DB+/- RX+/-

RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

GBE0_MDI0-

A12

I/O Analog

3.3V max Suspend

A10

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI1+/-

GBE0_MDI1-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI2+/-

GBE0_MDI2-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI3+/-

GBE0_MDI3-

I/O Analog

3.3V max Suspend

GBE0_ACT#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK1000#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA0_TX-

A17

O SATA

AC coupled on Module

AC Coupling capacitor

A19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA0_RX-

A20

I SATA

AC coupled on Module

AC Coupling capacitor

B16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA1_TX-

B17

O SATA

AC coupled on Module

AC Coupling capacitor

B19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA1_RX-

B20

I SATA

AC coupled on Module

AC Coupling capacitor

A22

O SATA

AC coupled on Module

SATA2_TX-

A23

O SATA

AC coupled on Module

A25

I SATA

AC coupled on Module

SATA2_RX-

A26

I SATA

AC coupled on Module

B22

O SATA

AC coupled on Module

SATA3_TX-

B23

O SATA

AC coupled on Module

B25

I SATA

AC coupled on Module

SATA3_RX-

B26

I SATA

AC coupled on Module

(S)ATA_ACT#

A28

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Connect to LED and

recommend

current limit resistor 220

Ω

to 3.3V

ATA (parallel and serial) or SAS activity indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A68

AC Coupling capacitor

PCIE_TX0-

A69

AC Coupling capacitor

B68

PCIE_RX0-

B69

A64

AC Coupling capacitor

PCIE_TX1-

A65

AC Coupling capacitor

B64

PCIE_RX1-

B65

A61

AC Coupling capacitor

PCIE_TX2-

A62

AC Coupling capacitor

B61

PCIE_RX2-

B62

A58

AC Coupling capacitor

PCIE_TX3-

A59

AC Coupling capacitor

B58

PCIE_RX3-

B59

A55

AC Coupling capacitor

PCIE_TX4-

A56

AC Coupling capacitor

B55

PCIE_RX4-

B56

A52

AC Coupling capacitor

PCIE_TX5-

A53

AC Coupling capacitor

B52

PCIE_RX5-

B53

D19

AC Coupling capacitor

PCIE_TX6-

D20

AC Coupling capacitor

C19

PCIE_RX6-

C20

D22

C22

PCIE_RX7-

C23

PCIE0_

A88

PCIE0_CLK_REF-

A89

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

D52

PEG_TX0-

D53

C52

PEG_RX0-

C53

D55

PEG_TX1-

D56

C55

PEG_RX1-

C56

D58

PEG_TX2-

D59

C58

PEG_RX2-

C59

D61

PEG_TX3-

D62

C61

PEG_RX3-

C62

D65

PEG_TX4-

D66

C65

PEG_RX4-

C66

D68

PEG_TX5-

D69

C68

PEG_RX5-

C69

D71

PEG_TX6-

D72

C71

PEG_RX6-

C72

D74

PEG_TX7-

D75

C74

PEG_RX7-

C75

D78

PEG_TX8-

D79

C78

PEG_RX8-

C79

D81

PEG_TX9-

D82

C81

PEG_RX9-

C82

D85

PEG_TX10-

D86

C85

PEG_RX10-

C86

D88

PEG_TX11-

D89

C88

PEG_RX11-

C89

D91

PEG_TX12-

D92

C91

PEG_RX12-

C92

D94

PEG_TX13-

D95

C94

PEG_RX13-

C95

D98

PEG_TX14-

D99

C98

PEG_RX14-

C99

D101

PEG_TX15-

D102

C101

PEG_RX15-

C102

PEG_LANE_RV#

D54

I CMOS

3.3V / 3.3V

PU 10K to 3.3V

PCI Express Graphics lane reversal input strap. Pull low on the Carrier

board to reverse lane order.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

DDI/SD

D26

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR0-/SDVO1_RED-

D27

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D29

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR1-/SDVO1_GRN-

D30

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D32

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR2-/SDVO1_BLU-

D33

Connect AC Coupling Capacitors 0.1uF to Device

DDI/S

D36

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR3-/SDVO1_CK-

D37

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

C25

DDI1_PAIR4-/SDVO1_INT-

C26

DDI/SDVO1_

C29

DDI1_PAIR5-/SDVO1_TVCLKIN-

C30

DDI/SDVO1_F

C15

DDI1_PAIR6-/SDVO1_FLDSTALL-

C16

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI1_HPD

C24

I CMOS

3.3V / 3.3V

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI1_DDC_AUX_SEL

D34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI1_CTRL and DDI1_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

D39

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR0-

D40

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D42

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR1-

D43

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D46

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR2-

D47

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D49

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR3-

D50

Connect AC Coupling Capacitors 0.1uF to Device

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high

DDI2_HPD

D44

I CMOS

3.3V / 3.3V

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI2_DDC_AUX_SEL

C34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI2_CTRL and DDI2_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

C39

DDI3_PAIR0-

C40

DDI

C42

DDI3_PAIR1-

C43

DDI

C46

DDI3_PAIR2-

C47

DDI

C49

DDI3_PAIR3-

C50

I/O PCIE

AC coupled on Module

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

DP AUX- function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high

DDI3_HPD

C44

I CMOS

3.3V / 3.3V

DDI Hot-Plug Detect

DDI3_DDC_AUX_SEL

C38

I CMOS

3.3V / 3.3V

Selects the function of DDI3_CTRL and DDI3_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

USB0+

A46

USB0-

A45

USB1+

B46

USB1-

B45

USB2+

A43

USB2-

A42

USB3+

B43

USB3-

B42

USB4+

A40

USB4-

A39

USB5+

B40

USB5-

B39

USB6+

A37

USB6-

A36

USB7+

B37

USB7-

B36

USB_0_1_OC#

B44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 0 and 1. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_2_3_OC#

A44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 2 and 3. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_4_5_OC#

B38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 4 and 5. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_6_7_OC#

A38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3_DU

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 6 and 7. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

AC Coupling capacitor

USB_SSTX0-

AC Coupling capacitor

USB_SSRX0-

AC Coupling capacitor

USB_SSTX1-

AC Coupling capacitor

USB_SSRX1-

D10

AC Coupling capacitor

USB_SSTX2-

AC Coupling capacitor

C10

USB_SSRX2-

D13

AC Coupling capacitor

USB_SSTX3-

D12

AC Coupling capacitor

C13

USB_SSRX3-

C12

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

A71

LVDS_A0-

A72

A73

LVDS_A1-

A74

A75

LVDS_A2-

A76

A78

LVDS_A3-

A79

A81

LVDS_A_CK-

A82

B71

LVDS_B0-

B72

B73

LVDS_B1-

B74

B75

LVDS_B2-

B76

B77

LVDS_B3-

B78

B81

LVDS_B_CK-

B82

LVDS_VDD_EN

A77

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel power circuit

LVDS panel power enable

LVDS_BKLT_EN

B79

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel backlight power circuit.

LVDS panel backlight enable

LVDS_BKLT_CTRL

B83

O CMOS

3.3V / 3.3V

Connect to brightness control of LVDS panel backlight power circuit.

LVDS panel backlight brightness control

LVDS_I2C_CK

A83

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC clock of LVDS panel

I2C clock output for LVDS display use

LVDS_I2C_DAT

A84

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC data of LVDS panel

I2C data line for LVDS display use

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

O CMOS

3.3V / 3.3V

LPC frame indicates the start of an LPC cycle

LPC_DRQ0#

PU 10K to 3.3V

LPC_DRQ1#

PU 10K to 3.3V

LPC_SERIRQ

A50

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

LPC serial interrupt

LPC_CLK

B10

O CMOS

3.3V / 3.3V

LPC clock output - 24MHz nominal

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

SPI_CS#

B97

O CMOS

3.3V Suspend/3.3V

Connect to Carrier Board SPI Device CS# pin

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

SPI_MISO

A92

I CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SO pin

Data in to Module from Carrier SPI

SPI_MOSI

A95

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SI pin

Data out from Module to Carrier SPI

SPI_CLK

A94

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SCK pin

Clock from Module to Carrier SPI

SPI_POWER

A91

3.3V Suspend/3.3V

Power supply for Carrier Board SPI – sourced from Module – nominally

3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.

Carriers shall use less than 100mA of SPI_POWER. SPI_POWER

shall only be used to power SPI devices on the Carrier Board.

BIOS_DIS0#

A34

BIOS_DIS1#

B88

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

VGA_RED

B89

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Red for monitor. Analog output

VGA_GRN

B91

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Green for monitor. Analog output

VGA_BLU

B92

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Blue for monitor. Analog output

VGA_HSYNC

B93

O CMOS

3.3V / 3.3V

Connect to VGA connector with a3.3V Buffer IC to isolate PCH & Display Device

Horizontal sync output to VGA monitor

VGA_VSYNC

B94

O CMOS

3.3V / 3.3V

Connect to VGA connector with a 33V Buffer IC to isolate PCH & Display Device

Vertical sync output to VGA monitor

VGA_I2C_CK

B95

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT

B96

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC data line.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

SER0_TX

A98

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 0 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER0_RX

A99

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 0 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_TX

A101

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 1 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_RX

A102

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 1 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

I2C_CK

B33

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

General purpose I2C port clock output

I2C_DAT

B34

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

General purpose I2C port data I/O line

SPKR

B32

O CMOS

3.3V / 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.

This port provides the PC beep signal and is mostly intended for

debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

Output indicating that a watchdog time-out event has occurred.

FAN_PWMOUT

B101

O OD CMOS

3.3V / 3.3V

Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

FAN_TACHIN

B102

I OD CMOS

3.3V / 3.3V

PU 47K to 3V3

Fan tachometer input for a fan with a two pulse output.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

TPM_PP

A96

I CMOS

3.3V / 3.3V

Default NA, PD 4.7K when stuff TPM chip

Trusted Platform Module (TPM) Physical Presence pin. Active high.

TPM chip has an internal pull down. This signal is used to indicate

Physical Presence to the TPM.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

PU 4.7K to 3V3_SB

A falling edge creates a power button event. Power button events can

be used to bring a system out of S5 soft off and other suspend states,

as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU

NC PU 4.7K to 3V3_SB

Reset button input. Active low request for Module to reset and reboot.

May be falling edge sensitive. For situations when SYS_RESET# is

not able to reestablish control of the system, PWR_OK or a power

cycle may be used.

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Reset output from Module to Carrier Board. Active low. Issued by

Module chipset and may result from a low SYS_RESET# input, a low

PWR_OK input, a VCC_12V power input that falls below the minimum

specification, a watchdog timeout, or may be initiated by the Module

software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

PU 10K to 5V and PD 20K

Power OK from main power supply. A high value indicates that the

power is good. This signal can be used to hold off Module startup to

allow Carrier based FPGAs or other configurable devices time to be

programmed.

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Suspend to RAM state. Active low output. An

inverted copy of SUS_S3# on the Carrier Board may be used to

enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

PD 10K to GND

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 1K to 3V3_DU

PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU

General purpose wake up signal. May be used to implement wake-up

on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 10K to 3V3_DU

Indicates that external battery is low.

This port provides a battery-low signal to the Module for orderly

transitioning to power saving or power cut-off ACPI modes.

LID#

A103

I OD CMOS

3.3V Suspend/12V

PU 47K to 3V3_DU_EC

LID switch. Low active signal used by the ACPI operating system for a LID switch.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SLEEP#

B103

I OD CMOS

3.3V Suspend/12V

PU 10K to 3V3_DU_EC

Sleep button. Low active signal used by the ACPI operating system to bring the

system to sleep state or to wake it up again.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

THRM#

B35

I CMOS

3.3V / 3.3V

PU 10K to 3V3

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK

B13

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus Alert – active low input can be used to

generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

PU 10K to 3.3V

GPI1

A63

PU 10K to 3.3V

GPI2

A67

PU 10K to 3.3V

GPI3

A85

PU 10K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail / Tolerance

WL968

Carrier Board

Description

VCC_12V

A104~A109

B104~B109

C104~C109

D104~D109

Power

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

VCC_5V_SBY

B84~B87

Power

Standby power input: +5.0V nominal. If VCC5_SBY is used, all

available VCC_5V_SBY pins on the connector(s) shall be used. Only

used for standby and suspend functions. May be left unconnected if

these functions are not used in the system design.

VCC_RTC

A47

Power

Real-time clock circuit-power input. Nom3.0V.

GND

A1, A11, A21, A31,

A41, A51, A57, A60,

A66, A70, A80, A90,

A100, A110, B1,

B11, B21 ,B31, B41,

B51, B60, B70, B80,

B90, B100, B110,

C1, C2, C5, C8, C11,

C14, C21, C31, C41,

C51, C60, C70, C73,

C76, C80, C84, C87,

C90, C93, C96,

C100, C103, C110,

D1, D2, D5, D8,

D11, D14, D21,

D31, D51, D60,

D67, D70, D73,

D76, D80, D84,

D87, D90, D93,

D96, D100, D103,

D110

Power

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier

Board GND plane.

Connect to LPC device

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Default NA(Request by BOM option)

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Pin Types

I Input to the Module

O Output from the Module

I/O Bi-directional input / output signal

OD Open drain output

AC coupled off Module

Serial Digital Video Field Stall input differential pair.

O PCIE

AC coupled off Module

DDI 1 Pair 3 differential pairs/Serial Digital Video B clock output differential pair

I PCIE

AC coupled off Module

Serial Digital Video TVOUT synchronization clock input differential pair.

AC coupled off Module

Selection straps to determine the BIOS boot device.

The Carrier should only float these or pull them low, please refer to

below table for strapping options of BIOS disable signals.

LVDS Channel B differential clock

LPC Signals Descriptions

O PCIE

AC coupled off Module

DDI 3 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 3 differential pairs

DDI 3 Pair 2 differential pairs

O PCIE

DDI 3 Pair 1 differential pairs

DDI3_CTRL

C36

DDI3_CTRLDATA_AUX-

C37

O PCIE

AC coupled off Module

DDI 2 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 3 Pair 3 differential pairs

AC coupled off Module

DDI Signals Descriptions

O PCIE

AC coupled off Module

DDI 1 Pair 0 differential pairs/Serial Digital Video B red output differential pair

I PCIE

3.3V / 3.3V

LPC serial DMA request

SPI Signals Descriptions

O PCIE

AC coupled off Module

DDI 2 Pair 2 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 1 differential pairs

O PCIE

AC coupled off Module

DDI2_CTRL

C32

DDI2_CTRLDATA_AUX-

C33

DDI1_CTRL/SDVO1_CTRLCLK D15

DDI1_CTRLDATA_AUX-

/SDVO1_CTRLDATA

D16

AC coupled off Module

DDI 1 Pair 2 differential pairs/Serial Digital Video B blue output differential pair

O PCIE

AC coupled off Module

DDI 1 Pair 1 differential pairs/Serial Digital Video B green output differential pair

Power and GND Signal Descriptions

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

I/O CMOS

3.3V / 3.3V

I CMOS

3.3V / 3.3V

General purpose input pins.

Pulled high internally on the Module.

Power and System Management Signals Descriptions

GPIO Signals Descriptions

O CMOS

Serial Digital Video B interrupt input differential pair.

General purpose output pins.

Upon a hardware reset, these outputs should be low.

VGA Signals Descriptions

3.3V / 3.3V

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

LPC multiplexed address, command and data bus

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel B differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,

LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential clock

O LVDS

LVDS

Connect to LVDS connector

Serial Interface Signals Descriptions

Miscellaneous Signal Descriptions

I CMOS

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 7

LVDS Signals Descriptions

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,

LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Module

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 2

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 1

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 6

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 4

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 3

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 5

USB Signals Descriptions

I/O USB

3.3V Suspend/3.3V

Connect 90

�

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 14

PCI Express Graphics receive differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 14

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 15

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 15

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 11

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 11

PCI Express Graphics receive differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 8

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 8

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 6

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 5

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 7

AC coupled on Module

PCI Express Graphics transmit differential pairs 7

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 6

PCI Express Graphics transmit differential pairs 4

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 3

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 2

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 3

PCI Express Graphics receive differential pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

I PCIE

PCI Express Graphics transmit differential pairs 2

PEG Signals Descriptions

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 0

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 1

AC coupled off Module

PCI Express Graphics receive differential pairs 1

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Receive Pairs 7

PCIe CLK Buffer

or slot

Reference clock output for all PCI Express and PCI Express Graphics

lanes.

PCI Express Differential Receive Pairs 6

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 7

PCI Express Differential Transmit Pairs 4

PCI Express Differential Receive Pairs 2

PCI Express Differential Transmit Pairs 6

PCI Express Differential Transmit Pairs 3

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 5

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 5

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

AC coupled on Module

PCI Express Differential Transmit Pairs 1

PCI Express Differential Receive Pairs 1

PCI Express Differential Receive Pairs 3

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 0

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 2

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 0

I PCIE

AC coupled off Module

O PCIE

AC97/HDA Signals Descriptions

Serial TDM data inputs from up to 2 CODECs.

Gigabit Ethernet Signals Descriptions

PCI Express Lanes Signals Descriptions

Serial ATA or SAS Channel 0 transmit differential pair.

Connect to SATA0 Conn RX pin

Serial ATA or SAS Channel 0 receive differential pair.

Connect to SATA1 Conn TX pin

Default NA (Request by BOM option)

Serial ATA or SAS Channel 3 transmit differential pair.

Serial ATA or SAS Channel 3 receive differential pair.

Default NA (Request by BOM option)

Serial ATA or SAS Channel 2 receive differential pair.

Serial ATA or SAS Channel 2 transmit differential pair.

Connect to SATA1 Conn RX pin

Serial ATA or SAS Channel 1 receive differential pair.

SATA Signals Descriptions

Connect to SATA0 Conn TX pin

Serial ATA or SAS Channel 1 transmit differential pair.

Ref

Line

Bios

Entry

SPI

Descriptor

Carrier

SPI_CS#

Chipset

SPI CS0#

Destination

Chipset

SPI CS1#

Destination

BIOS

DIS0#

BIOS

DIS1#

Module

SPI0/SPI1

SPI1

(Default)

SPI0

High

Carrier

Carrier

(Default)

Module

(Default)

Module

Module

(Default)

Module

Carrier FWH

SPI0/SPI1

(Default)

SPI0/SPI1

DDI2 is option function

Summary of Contents for WL968

Page 1: ...www dfi com Chapter 1 Introduction 1 WL968 A 617 M 2046 ver a_MP_12 1420_13 37 COM Express Compact Module User s Manual ...

Page 2: ...OM Express ModuleTM Base Specification http www picmg org FCC and DOC Statement on Class B This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC rules These limits are designed to provide reason able protection against harmful interference when the equipment is operated in a residential installation This equipment generates u...

Page 3: ...ard 22 Installing the COM Express Debug Card Optional 24 Chapter 4 BIOS Setup 26 Overview 26 Insyde BIOS Setup Utility 27 Main 27 Advanced 27 ACPI Configuration 28 CPU Configuration 29 Power Performance 29 PCH FW Configuration 30 Trusted Computing 32 PTN3460 Configuration 33 IT8528 Super IO Configuration 34 IT8528 Super IO Configuration Serial Port 1 2 Configuration 34 Serial Port Console Redirect...

Page 4: ...e You must take extra care in han dling them to ensure against electrostatic build up 1 To prevent electrostatic build up leave the system board in its anti static bag until you are ready to install it 2 Wear an antistatic wrist strap 3 Do all preparation work on a static free surface 4 Hold the device only by its edges Be careful not to touch any of the components contacts or connections 5 Avoid ...

Page 5: ...package may not come similar to the information listed above This may differ in accordance with the sales region or models in which it was sold For more information about the standard package in your region please contact your dealer or sales representative Before Using the System Board Before using the system board prepare basic system components If you are installing the system board in a new sy...

Page 6: ... DP resolution up to 4096x2304 60Hz Triple Displays VGA LVDS DDI DDI eDP DDI EXPANSION eMMC 1 x 8GB 16GB 32GB 64GB 128GB eMMC 5 1 available upon request Interface 6 PCIe x1 or 2 PCIe x1 1 PCIe x4 or 3 PCIe x1 2 PCIe x2 support up to 5 devices and 7 lanes 1 x LPC 1 x I2C 1 x SMBus 2 x UART TX RX AUDIO Interface HD Audio ETHERNET Controller 1 x Intel I219LM with iAMT12 x PCIe 10 100 1000Mbps I O USB...

Page 7: ...e demand for business and home entertainment applications Serial ATA Serial ATA is a storage interface that is compliant with SATA 1 0a specification With speed of up to 6Gb s SATA 3 0 it improves hard drive performance faster than the standard parallel ATA whose data transfer rate is 100MB s The bandwidth of the SATA 3 0 will be limited by carrier board design Gigabit LAN The Intel I219LM Gigabit...

Page 8: ...ed Basic Compact Mini 74 20 80 00 91 00 121 00 151 00 Common for all Form Factors Extended only Basic only Compact only Compact and Basic only Mini only COM Express Module Standards The figure below shows the dimensions of the different types of COM Express modules The dimension of COM Express Compact module is 95mm x 95mm ...

Page 9: ... B A A B SDIO muxed on GPIO 0 0 1 General Purpose I O 8 8 8 1 1 1 s u B M S B A 1 1 1 C 2 I B A A B Watchdog Timer 0 1 1 A B Speaker Out 1 1 1 A B External BIOS ROM Support 0 1 2 A B Reset Functions 1 1 1 A B A B T 1 1 0 n o i t c e t o r P l a m r e h A B Battery 1 1 0 m r a l A w o L A B Suspend Wake Sig 1 3 0 s l a n A B Power Button Support 1 1 1 1 1 1 d o o G r e w o P B A 4 4 4 s t c a t n o...

Page 10: ...allation Board Layout Top View Bottom View iTE IT8528VG TPM optional SPI Flash BIOS Intel BGA 1528 Intel I219LM NXP PTN3460 Chrontel CH7517 CPU Fan 3 1 Standby Power LED SO_DIMM1 COM Express Connector C1 D1 C110 D110 B1 B110 A1 A110 COM Express Connector SO_DIMM1 ...

Page 11: ...rap and attaching it to a metal part of the system chassis If a wrist strap is unavailable establish and maintain contact with the system chassis throughout any procedures requiring ESD protection Important When the Standby Power LED is red it indicates that there is power on the board Power off the PC then unplug the power cord prior to installing any devices Failure to do so will cause severe da...

Page 12: ...g fan 3 1 Sense 12V Ground COM Express Connectors The COM Express connectors are used to interface the WL968 COM Express board to a carrier board Connect the COM Express connectors located on the solder side of the board to the COM Express connectors on the carrier board Refer to the Installing WL968 onto a Carrier Board section for more information Refer to the following pages for the pin functio...

Page 13: ... RSVD D27 DDI1_PAIR0 C82 NA D82 NA A28 S ATA_ACT B28 NA A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C28 RSVD D28 RSVD C83 RSVD D83 RSVD A29 AC HDA_SYNC B29 AC HDA _SDIN1 A84 LVDS_I2C_DAT B84 VCC_5V_SBY C29 NA D29 DDI1_PAIR1 C84 GND D84 GND A30 AC HDA _RST B30 AC HDA _SDIN0 A85 GPI3 B85 VCC_5V_SBY C30 NA D30 DDI1_PAIR1 C85 NA D85 NA A31 GND FIXED B31 GND FIXED A86 RSVD B86 VCC_5V_SBY C31 GND FIXED D31 GND F...

Page 14: ...7 O SATA AC coupled on Module AC Coupling capacitor SATA1_RX B19 I SATA AC coupled on Module AC Coupling capacitor SATA1_RX B20 I SATA AC coupled on Module AC Coupling capacitor SATA2_TX A22 O SATA AC coupled on Module NA SATA2_TX A23 O SATA AC coupled on Module NA SATA2_RX A25 I SATA AC coupled on Module NA SATA2_RX A26 I SATA AC coupled on Module NA SATA3_TX B22 O SATA AC coupled on Module NA SA...

Page 15: ...eive differential pair Default NA Request by BOM option Serial ATA or SAS Channel 2 receive differential pair Serial ATA or SAS Channel 2 transmit differential pair Connect to SATA1 Conn RX pin Serial ATA or SAS Channel 1 receive differential pair SATA3_RX B25 I SATA AC coupled on Module NA SATA3_RX B26 I SATA AC coupled on Module NA S ATA_ACT A28 I O CMOS 3 3V 3 3V PU 10K to 3 3V Connect to LED a...

Page 16: ...NA PEG_TX11 D88 NA PEG_TX11 D89 NA PEG_RX11 C88 NA PEG_RX11 C89 NA PEG_TX12 D91 NA PEG_TX12 D92 NA PEG_RX12 C91 NA PEG_RX12 C92 NA PEG_TX13 D94 NA PEG_TX13 D95 NA PEG_RX13 C94 NA PEG_RX13 C95 NA PEG_TX14 D98 NA PEG_TX14 D99 NA PEG_RX14 C98 NA PEG_RX14 C99 NA PEG_TX15 D101 NA PEG_TX15 D102 NA PEG_RX15 C101 NA PEG_RX15 C102 NA PEG_LANE_RV D54 I CMOS 3 3V 3 3V PU 10K to 3 3V PCI Express Graphics lane...

Page 17: ...SB_SSRX2 C9 USB_SSTX3 D13 AC Coupling capacitor USB_SSTX3 D12 AC Coupling capacitor USB_SSRX3 C13 USB_SSRX3 C12 Signal Pin Module Pin Type Pwr Rail Tolerance WL968 Carrier Board Description LVDS_A0 A71 LVDS_A0 A72 LVDS_A1 A73 LVDS_A1 A74 LVDS_A2 A75 LVDS_A2 A76 LVDS_A3 A78 LVDS_A3 A79 LVDS_A_CK A81 LVDS_A_CK A82 LVDS_B0 B71 O PCIE AC coupled on Module Connect 90 100MHz Common Choke in series and E...

Page 18: ...O CMOS 3 3V 3 3V Connect to VGA connector with a 33V Buffer IC to isolate PCH Display Device Vertical sync output to VGA monitor VGA_I2C_CK B95 I O OD CMOS 3 3V 3 3V PU 2 2K to 3 3V Connect to VGA connector with a 3 3V to 5V Level shift circuit DDC clock line I2C port dedicated to identify VGA monitor capabilities VGA_I2C_DAT B96 I O OD CMOS 3 3V 3 3V PU 2 2K to 3 3V Connect to VGA connector with ...

Page 19: ...ng edge creates a power button event Power button events can be used to bring a system out of S5 soft off and other suspend states as well as powering the system down SYS_RESET B49 I CMOS 3 3V Suspend 3 3V PU 10K to 3V3_DU NC PU 4 7K to 3V3_SB Reset button input Active low request for Module to reset and reboot May be falling edge sensitive For situations when SYS_RESET is not able to reestablish ...

Page 20: ...rrier Board Active low Issued by Module chipset and may result from a low SYS_RESET input a low PWR_OK input a VCC_12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the Module software PWR_OK B24 I CMOS 3 3V 3 3V PU 10K to 5V and PD 20K Power OK from main power supply A high value indicates that the power is good This signal can be used to hold of...

Page 21: ...er LED SO_DIMM1 Cooling Option Heat Sink 1 denotes the location of the thermal pad designed to contact the corresponding components that are on the WL968 Top View of the Heat Sink Important Remove the plastic covering from the thermal pads prior to mounting the heat sink onto the WL968 Note The system board used in the following illustrations may not resemble the actual board These illustrations a...

Page 22: ...ess WL968 down firmly to seat it in the COM Express connectors of the carrier board Note The illustration above shows the pressing points of the module onto the carrier board Be careful when pressing the module to avoid damages to the connectors 1 Grasp WL968 by its edges and position it on top of the carrier board with the mounting holes of WL968 aligning with the standoffs on the carrier board T...

Page 23: ...www dfi com Chapter 1 Introduction 23 3 Use the provided mounting screws to secure WL968 with heat sink to the carrie board The photo below shows the locations of the long mounting screws Long screws ...

Page 24: ...esigned for COM Express Compact modules to debug and display signals and codes of COM Express modules COMe LINK1 Bottom view Top view COMe DEBUG Connector COM Express Connectors 2 Connect the COMe DEBUG card to COMe LINK1 via a cable COMe DEBUG COMe LINK1 Cable COMe DEBUG COM Express Connectors COMe LINK1 2 Connector Port 80 Display LPC COM Express Signal Display Power Reset Sleep LID control COM ...

Page 25: ... debug card onto the carrier board COMe LINK1 Carrier Board 4 Then use the instructions from the previous section to install SU968 and heat sink on the top of the COMe LINK1 debug card Screws COMe DEBUG Side View of the Module Debug Card and Carrier Board COMe LINK1 Carrier Board WL968 ...

Page 26: ...does not require an operating system to run After you power up the system the BIOS message appears on the screen and the memory count begins After the memory test the message Press DEL to run setup will appear on the screen If the message disappears before you respond restart the system or press the Reset button You may also restart the system by pressing the Ctrl Alt and Del keys simultaneously N...

Page 27: ...SC Exit Security Advanced Chipset Boot Save Exit Main Version 2 20 1275 Copyright C 2020 American Megatrends Inc Set the Date Use Tab to switch between Date ele ments Default Ranges Year 2005 2099 Months 1 12 Days dependent on month Project Name BIOS Version EC Version FSP version RC version Intel R Core TM i5 8365UE CPU 1 60GHz ID Stepping L1 Data Cache L1 Instruction Cache L2 Cache L3 Cache Numb...

Page 28: ... of the day hour 00 23 minute 00 59 second 00 59 Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Version 2 20 1275 Copyright C 2020 American Megatrends Inc Advanced Enable or disable System wake on alarm event When enabled System will wake on the hr min sec...

Page 29: ...only be displayed when EIST is enabled C States Enable or disable CPU Power Management It allows CPU to enter C states when it s idle and nothing is executing Note Some of the fields may not be available when the features are not supported by the equipped CPU Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous V...

Page 30: ...anageability features This option disables enables Manageability Features support in FW To disable support platform must be in an unprovisioned state first AMT BIOS Features When disabled AMT BIOS features are no longer supported and user is no longer able to ac cess MEBx Setup This option does not disable manageability features in FW ME Unconfig on RTC Clear When disabled ME will not be unconfigu...

Page 31: ...r Real Force Secure Erase Enable or disable Force Secure Erase on next boot AMT Confuguration OEM Flags Settings Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Version 2 20 1275 Copyright C 2020 American Megatrends Inc Advanced OEMFlag Bit 6 Hide Unconfigu...

Page 32: ...lect Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Version 2 20 1275 Copyright C 2020 American Megatrends Inc Advanced TPM20 Device Found Firmware Version Vendor Security Device Support Pending operation 403 1 INTC Enable None Enables or Disables BIOS support for security de vice O S will not show Security Device TCG EFI ...

Page 33: ...can Megatrends Inc Advanced Enabled or Disabled PTN3460 LCD Features PTN3460 Function LCD Panel Type LCD Panel Color Depth Disabled 1024x768 24 Bit PTN3460 Function Enable or disable PTN3460 LCD features The following fields are only configurable when this field is enabled LCD Panel Type Select the resolution of the LCD Panel 800X480 800X600 1024X768 1366X768 1280X1024 1280X768 1920X1080 or 1600X9...

Page 34: ...te The sub menus are detailed in following sections Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Version 2 20 1275 Copyright C 2020 American Megatrends Inc Advanced Serial Port 1 Configuration Serial Port Device Settings Change Settings Enabled IO 3F8h I...

Page 35: ...ngs Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Version 2 20 1275 Copyright C 2020 American Megatrends Inc Advanced Emulation ANSI Extend ed ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color funtion keys etc VT UTF8 Users UTF8 en ...

Page 36: ...B Support Enabled Enable Legacy USB support Disabled Keep USB devices available only for EFI applications Auto Disable Legacy support if no USB devices are connected XHCI Hand off Enable or disable XHCI Hand off USB Mass Storage Driver Support Enable or disable USB Mass Storage Driver Support Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change...

Page 37: ...ount 4 SYS Smart Fan Control Boundary 1 Boundary 2 Boundary 3 Boundary 4 Fan Speed Count 1 Fan Speed Count 2 Fan Speed Count 3 Fan Speed Count 4 Enable 30 40 50 60 35 60 80 100 Enable 30 40 50 60 35 60 80 100 PC Health Status Smart Fan Function Smart Fan is a fan speed moderation strategy dependent on the current system temperature When the system temperature goes higher than the Boundary setting ...

Page 38: ...PXE Support Ipv6 PXE Support PXE boot wait time Media detect count Enabled Disabled Disabled 0 1 Network Stack Enable or disable UEFI network stack The following fields will appear when this field is en abled Ipv4 PXE Support Enable or disable IPv4 PXE boot support If disabled IPv4 PXE boot support will not be avail able Ipv6 PXE Support Enable or disable IPv6 PXE boot support If disabled IPv6 PXE...

Page 39: ... Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F9 Optimized Defaults F10 Save Exit ESC Exit Chipset Version 2 20 1275 Copyright C 2020 American Megatrends Inc Primary Display Select which of IGFX PEG PCI Graphics device to be the primary display Internal Graphics Keep IGFX enabled based on the setup optio...

Page 40: ...nable Enable or disable integrated LAN to wake the system Above 4GB MMIO BIOS assignment Switch MemoryMappedIO BIOS assignment above 4GB Max TOLUD Assign a value or set Dynamic to automatically adjust TOLUD based on largest MMIO length Note The sub menus are detailed in following sections Aptio Setup Utility Copyright C 2019 American Megatrends Inc Select Screen Select Item Enter Select Change Opt...

Page 41: ...0 American Megatrends Inc SATA And RST Configuration SATA Controller s SATA Controller Speed SATA Mode Selection Serial ATA Port 0 Port 0 Hot Plug Serial ATA Port 1 Port 1 Hot Plug Serial ATA Port 2 Port 2 Hot Plug Enabled Auto AHCI Empty Enabled Disabled Empty Enabled Disabled Empty Enabled Disabled Enable or disable SATA Device SATA Controller s This field is used to enable or disable the Serial...

Page 42: ...s F10 Save Exit ESC Exit Chipset Version 2 20 1275 Copyright C 2020 American Megatrends Inc Control Detection of the HD Audio device Disabled HDA will be un conditionally disabled Enabled HDA will be un conditionally enabled HD Audio Subsystem Confi guration Settings HD Audio Enabled HD Audio Control the detection of the HD Audio device Disabled HDA will be unconditionally disabled Enabled HDA wil...

Page 43: ...rican Megatrends Inc Secure Boot feature is Ac tive if Secure Boot is Ena bled Platfom Key PK is enrolled and the System is in User mode The mode change requires platform reset System Mode Secure Boot Secure Boot Mode Restore Factory Keys Reset To Setup Mode Setup Disabled Not Active Custom Secure Boot The Secure Boot store a database of certificates in the firmware and only allows the OSes with a...

Page 44: ... 1275 Copyright C 2020 American Megatrends Inc Advanced Save Options Save Changes and Reset Discard Changes and Reset Restore Defaults Boot Override Save Setting to file Restore Setting from file Reset the system after saving the changes Save Changes and Reset To save the changes select this field and then press Enter A dialog box will appear Select Yes to reset the system after saving all changes...

Page 45: ...m this system board and used on another system board of the same model 2 The BIOS SPI ROM on this system board must be the original equipment from the factory and cannot be used to replace one which has been utilized on other system boards 3 If you do not follow the methods above the Intel Management Engine will not be updated and will cease to be effective Note a You can take advantage of flash t...

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