DFI NP951-B16C, User Manual

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3
BIOS Setup
CAS Latency Time
This field is used to select the local memory clock periods.
DRAM RAS# to CAS# Delay
This field is used to select the latency between the DRAM active command and
the read/write command.
DRAM RAS# Precharge
This field is used to select the idle clocks after issuing a precharge command to
the DRAM.
Precharge Delay (tRAS)
The options are Auto and 4 to15.
System Memory Frequency
This field is used to select the frequency of the system memory.
SLP_S4# Assertion Width
The options are 1 to 2 Sec., 2 to 3 Sec., 3 to 4 Sec. and 4 to 5 Sec.
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is enabled. The
larger the range of the Cache RAM, the higher the efficiency of the system.
Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will allow ac-
cess to video BIOS addresssed at C0000H to C7FFFH to be cached, if the cache
controller is also enabled. The larger the range of the Cache RAM, the faster the
video performance.
Memory Hole At 15M-16M
In order to improve system performance, certain space in memory can be re-
served for ISA cards. This memory must be mapped into the memory space
below 16MB. When enabled, the CPU assumes the 15-16MB memory range is
allocated to the hidden ISA address range instead of the actual system DRAM.
When disabled, the CPU assumes the 15-16MB address range actually contains
DRAM memory. If more than 16MB of system memory is installed, this field must
be disabled to provide contiguous system memory.