DFI NP101-D16C, User Manual

Page: 65 / 141

65
3
BIOS Setup
Advanced Chipset Features
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
These items should not
be altered unless necessary. The default settings have been chosen
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
DRAM Timing Selectable
This field is used to select the timing of the DRAM.
By SPD The EEPROM on a DIMM has SPD (Serial Pres-
ence Detect) data structure that stores informa-
tion about the module such as the memory type,
memory size, memory speed, etc. When this op-
tion is selected, the system will run according to
the information in the EEPROM. This option is the
default setting because it provides the most sta-
ble condition for the system. The “CAS Latency
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
x CAS Latency Time
x DRAM RAS# to CAS# Delay
x DRAM RAS# Precharge
x Precharge Delay <tRAS>
x System Memory Frequency
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
X
PCI Express Root Port Func
** VGA Setting **
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
Panel Scaling
Panel Number
Item Help
Menu Level
XX
By SPD
Auto
Auto
Auto
Auto
Auto
4 to 5 Sec.
Enabled
Disabled
Disabled
Press Enter
8MB
DVMT
128MB
Auto
Auto
3 : 1024*768 (18 bit)
↑↓→←
: Move Enter: Select F1: General Help +/-/PU/PD: Value F10: Save ESC: Exit
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
The settings on the screen are for reference only. Your version may not be
identical to this one.