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45
Chipset Features Setup
This section gives you instructions on how to configure the system
based on the specific features of the chipset. The chipset manages bus
speeds and access to system memory resources such as DRAM and
external cache. It also coordinates communications between the con-
ventional ISA bus and the PCI bus. These items should not be altered
unless necessary. Depending on your add-in boards, you may not or
should not enable some of these features. The default settings have
been chosen because they provide optimum operating conditions for
your system.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
CAS Width For Read FPM/EDO
CAS Address Setup (Read)
CAS Width For Write
CAS Address Setup (Burst)
CAS Address Setup (Write)
RAS Address Hold Time
RAS Precharge Time
RAS to CAS delay
DRAM R To W Arbitration
CPU Bus Arbitration
CPU to PCI Write Buffer
Combine Memory Write
Write Buffer Read Around
Shadow RAM Cacheable
ISA DMA Wait Cycle
ISA Command Delay
ISA Bus Wait State
PCI 2.1 Compliant
ISA Memory Post Write
: Enabled
: 3T/2T
: 2T
: 2T
: 1T
: 1T
: 1T
: 3T
: 3T
: 2T
: Enabled
: Off
: Enabled
: Enabled
: Disabled
: Normal
: Disabled
: Normal
: Enabled
: Disabled
PCI Concurrency
PCI to DRAM Latency
PCI to DRAM Read Ahead
NA# Control on DRAM Write
NA# Control on Cache Read
Arbitration Parking
Lock PCI Bus On ISA DMA
Concurrent DRAM Write
Slow Loop Instruction
: Disabled
: Enabled
: Disabled
: Disabled
: Disabled
: Master
: Disabled
: Enabled
: Disabled
ESC
F1
F5
F6
F7
: Quit
: Help
: Old Values
: Load BIOS Defaults
: Load Setup Defaults
PU/PD/+/-
(Shift) F2
: Select Item
: Modify
: Color
↑ ↓ → ←