![background image](http://html1.mh-extra.com/html/dfi/cs101-h310/cs101-h310_user-manual_2491079027.webp)
www.d
fi
.com
27
Chapter 2 Hardware Installation
Chapter 2
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s tran-
sition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O com-
ponents within the system, which are typically provided by a Super I/O controller. Furthermore,
it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin fuctions of the LPC connector.
LPC
2 1
1413
Pin
Function
Pin
Function
1
CLK
2
LAD1
3
RST#
4
LAD0
5
FRAME#
6
3V3
7
LAD3
8
GND
9
LAD2
10
---
11
SERIRQ
12
GND
13
5VSB
14
5V
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
SMBus Connector
SMBus
1
2
5
GND
SMB_Data
SMB_CLK
3V3SB
SMB_Alert