26
Chapter 2
HARDWARE INSTALLATION
User's Manual |
CMS630
LPC Connector
X
Internal I/O Connectors
1
13
14
1
2
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transi-
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin functions of the LPC connector.
Pin Assignment
Pin Assignment
1
CLK
2
L_AD1
3
RST#
4
L_AD0
5
FRAME#
6
VCC3
7
LAD3
8
GND
9
LAD2
10
---
11
SERIRQ
12
GND
13
5V5B
14
5V
PS2
X
Internal I/O Connectors
1
Pin Assignment
Pin Assignment
1
KCLK
2
MCLK
3
KDAT
4
MDAT
5
GND
6
GND
7
---
8
GND
9
GND
10
GND
PS2 Pin Assignment
1
2
9
10
