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7-SEGMENT LED DISPLAY
The TINALab II FPGA development board utilizes four digit common-anode 7-segment
(numeric) LED displays that can be used during the test and debugging phase of a design. All of
these segments are active-low meaning that a LED will glow when a low logic level is applied to it.
Since the segment signals are also common, only one selected digit glow at a time, but if the digits
are switched one after the other fast in multiplexed mode all the digits seem to be still virtually.
NET "Digit0" LOC = "P51";
4-digit numeric LED display, digit1
NET "Digit1" LOC = "P50";
4-digit numeric LED display, digit2
NET "Digit2" LOC = "P48";
4-digit numeric LED display, digit3
NET "Digit3" LOC = "P47";
4-digit numeric LED display, digit4
NET "DISPA" LOC = "P43";
4-digit numeric LED display, segment A
NET "DISPB" LOC = "P41";
4-digit numeric LED display, segment B
NET "DISPC" LOC = "P29";
4-digit numeric LED display, segment C
NET "DISPD" LOC = "P27";
4-digit numeric LED display, segment D
NET "DISPE" LOC = "P26";
4-digit numeric LED display, segment E
NET "DISPF" LOC = "P42";
4-digit numeric LED display, segment F
NET "DISPG" LOC = "P40";
4-digit numeric LED display, segment G
NET "DISPDP" LOC = "P28";
4-digit numeric LED display, decimal point
RS232 SERIAL PORT
The TINALab FPGA development board provides an RS232 port that can be driven by the
Spartan-II FPGA. A subset of the RS232 signals are used on the Spartan-II development board to
implement this interface with the transmit and receive serial data streams (TXD and RXD,
respectively) as well as the flow control signals (RTS and CTS, respectively).
The board provides a DB-9 connection (J5) for a simple RS232 port. This board utilizes the Analog
Devices ADM3202 RS232 driver for driving the signals. The pin functions on the RS-232 port are
identical to those found on a PC serial port, so a null modem cable that swaps the TXD/RXD and
CTS/RTS lines is needed if the TINALab II FPGA board and PC are to communicate. The user
provides the RS232 UART code, which resides in the Spartan-II FPGA.
NET "RXD" LOC = "P120";
Data transmitted by FPGA
NET "TXD" LOC = "P122";
Data received by FPGA
NET "CTS" LOC = "P123";
Clear to send by the FPGA
NET "RTS" LOC = "P121";
Request to send to the FPGA
