Denon DSD-500, Service Manual

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66
ADSP21489 (U30)
ADSP21489 TOP View
ADSP21489 Block Diagram
Rev. A | Page 64 of 68 | April 2012
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SURFACE-MOUNT DESIGN
The exposed pad is required to be electrically and thermally
connected to GND. Implement this by soldering the exposed
pad to a GND PCB land that is the same size as the exposed pad.
The GND PCB land should be robustly connected to the GND
plane in the PCB for best electrical and thermal performance.
No separate GND pins are provided in the package.
Figure 53. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP
1
]
(SW-176-2)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 59 .
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
0.15
0.10
0.05
0.08
COPLANARITY
0.20
0.15
0.09
1.45
1.40
1.35
7°
3.5°
0°
VIEW A
ROTATED 90° CCW
0.27
0.22
0.17
0.75
0.60
0.45
0.50
BSC
LEAD PITCH
24.10
24.00 SQ
23.90
26.20
26.00 SQ
25.80
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
EXPOSED
PAD
1
44
1
44
45
89
88 45 88
132
89
132
176 133 176 133
PIN 1
1.60 MAX
1.00 REF
SEATING
PLANE
VIEW A
6.00
REF
21.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
“SURFACE-MOUNT DESIGN” IN
THIS DATA SHEET.
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©
2012 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 400 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Figure 1. Functional Block Diagram
Internal Memory I/F
Block 0
RAM/ROM
B0D
64-BIT
Instruction
Cache
5 Stage
Sequencer
PEx PEy
PMD
64-BIT
IOD0 32-BIT
EPD BUS 64-BIT
Core Bus
Cross Bar
DAI Routing/Pins
S/PDIF
Tx/Rx PCG
A-D
DPI Routing/Pins
SPI/B UART
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
AMI
SDRAM
CTL
EP
External Port Pin MUX
TIMER
1-0
SPORT
7-0
ASRC
3-0
PWM
3-0
DAG1/2
Core
Timer
PDAP/
IDP
7-0
TWI
IOD0 BUS
DTCP/
MTM
PCG
C-D
PERIPHERAL BUS
32-BIT
CORE
FLAGS/
PWM3-1
JTAG
Internal Memory
DMD
64-BIT
PMD 64-BIT
CORE
FLAGS
IOD1
32-BIT
PERIPHERAL BUS
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DPI Peripherals DAI Peripherals Peripherals
External
Port
SIMD Core
S
THERMAL
DIODE
FFT
FIR
IIR
SPEP BUS
DMD
64-BIT
FLAGx/IRQx/
TMREXP
WDT