Denon AirPlay AVR-3311CI, Service Manual

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183
SA7121 (HDMI : U4203)
SA7121 Block Diagram
SAA7120
SAA7121
MBH790
1 res.
SP
AP
LLC
VDDD1
VSSD1
RCV1
RCV2
MP7
MP6
MP5
MP4 MP3 MP2 MP1 MP0
V
DDD2
V
SSD2
RTCI
res.
SA
res.
2
3
4
5
6
7
8
9
10
11
33 VSSA2
VSSA1
VDDA3
VDDA2
VDDA1
Y
C
CVBS
res.
res.
res.
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44
TTX TTXRQ SDA SCL XCLK XTALI XTALO V
DDD3
V
DDA4
V
SSD3
RESET
43 42 41 40 39 38 37 36 35 34
handbook, full pagewidth
I
2
C-BUS
INTERFACE
DATA
MANAGER
ENCODER
SYNC
CLOCK
OUTPUT
INTERFACE
D
A
40 42 41 21
7 36 8 43 37 34 35 4 25, 28,
31
MP7
to
MP0
TTX
5, 18, 38 6, 17, 39
1, 20, 22,
23, 26, 29 2 19 3
30
27
24
32, 33
RESET SDA SCL
RCV1
RCV2
TTXRQ
XCLK
XTALO
XTALI
LLC
VDDA4
VSSA1
VSSA2
SA
CVBS
Y
C
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
VSSD1,
VSSD2,
VSSD3
VDDD1,
VDDD2,
VDDD3
VDDA1,
VDDA2,
VDDA3
res.
SP RTCI AP
clock
and timing
Y Y
C
CbCr
44
9 to 16
MBH787
SAA7120
SAA7121
1997 Jan 06 5
Philips Semiconductors Preliminary specification
Digital Video Encoder (ConDENC) SAA7120; SAA7121
V
SSD3
38 I digital ground 3
V
DDD3
39 I digital supply voltage 3
RESET 40 I reset input, active LOW; after reset is applied, all digital I/Os are in input mode;
the I
2
C-bus receiver waits for the START condition
SCL 41 I I
2
C-bus serial clock input
SDA 42 I/O I
2
C-bus serial data input/output
TTXRQ 43 O teletext request output, indicating when bit stream is valid
TTX 44 I teletext bit stream input
SYMBOL PIN I/O DESCRIPTION
Fig.2 Pin configuration.
handbook, full pagewidth
SAA7120
SAA7121
MBH790
1 res.
SP
AP
LLC
VDDD1
VSSD1
RCV1
RCV2
MP7
MP6
MP5
MP4 MP3 MP2 MP1 MP0
V
DDD2
V
SSD2
RTCI
res.
SA
res.
2
3
4
5
6
7
8
9
10
11
33 VSSA2
VSSA1
VDDA3
VDDA2
VDDA1
Y
C
CVBS
res.
res.
res.
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44
TTX TTXRQ SDA SCL XCLK XTALI XTALO V
DDD3
V
DDA4
V
SSD3
RESET
43 42 41 40 39 38 37 36 35 34