DDC NHi-15504 Instructions Manual Download Page 9 | Manualshive

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9

Default
The factory default configuration fot the IRQ line and RESET line is as follows:

JP4 (Open)

•

•

•

JP14 (Open)

•

•

•

JP6 (Open)

•

•

•

JP8 (3.3V)

•

•

•

JP9 (C3 Open)

•

•

•

RESET/IRQ Reference Circuit:

PCI-A15

RST_L

JP6

Ground

PCI-A6
INTA_L

JP4

IRQ

+3.3v

+5.0v

JP8

R12
3.3K

JP9

C3

330 OHM

MRST_L

JP14

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Summary of Contents for NHi-15504

Page 1: ...ded in this document is believed to be accurate however no responsibility is assumed by NATIONAL HYBRID INC for its use and no license or rights are granted by implication or otherwise in connection t...

Page 2: ...atures 5 1 1 3 Bus Monitor Features 5 1 2 Description 6 2 0 Inspection 6 2 1 System Requirements 6 2 2 Installation 7 2 3 Hardwired RT Address Jumpers 7 2 4 Transmitter and SSF Jumpers 8 2 5 Master Re...

Page 3: ...NAL FEATURES Multi Protocol Interface Operates from 20 Mhz clock Appears to host as a Dual Port Double Buffered 64K x 16 SRAM Footprint less than 1 square inch Ensures integrity of all shared data and...

Page 4: ...ry Alternate Bus then Current Bus Programmable response timeout of 14 18 26 or 42 microseconds Programmable Intermessage Gap Time up to 4 mS with 2uS resolution Programmable Synchronous Message Time u...

Page 5: ...er algorithm which ensures high noise immunity and a low error rate Software RT Address Lockout MDC3818 Status Response Error Handling Status Bit Definition Mode Code Operation Separate Broadcast Tabl...

Page 6: ...on self test of the PC or by any other process 2 0 Inspection The card has been thoroughly tested and inspected before shipment After removing the card from the packing container please retain the co...

Page 7: ...are Do NOT let Windows look for a driver Direct Windows to the subdirectory where the driver resides C NHi15504pci in this example NOTE For windows NT which is not Plug n Play follow the installation...

Page 8: ...ND IRQ JUMPERS Definitions Ref Reset IRQ circuit below JP4 This jumper determines whether or not an External INTA is allowed from the PCI bus JP14 This jumper determines whether or not a resistor 300...

Page 9: ...nfiguration fot the IRQ line and RESET line is as follows JP4 Open JP14 Open JP6 Open JP8 3 3V JP9 C3 Open RESET IRQ Reference Circuit PCI A15 RST_L JP6 Ground PCI A6 INTA_L JP4 IRQ 3 3v 5 0v JP8 R12...

Page 10: ...ESS CONTENTS OPERATION R W Base 0 Control Register R W Base 1 RT Message Pointer Table Address Register R W Base 2 Basic Status Register R W Base 3 INTERRUPT MASK lower byte R W Base 3 INTERRUPT VECTO...

Page 11: ...ternal RT Address Buffer lower byte R Base 30 Reserved Base 31 BC MT Interrupt Vector R W In order to write to addresses 23 24 and 25 the Terminal must be in loopback in the RT mode see Control Regist...

Page 12: ...e Subaddress 1 Up To 63 Pointers Per Message MESSAGE POINTER TABLE INDEX Index T R Subaddress Mode Code Command 0 Not Used 1 30 0 1 30 Receive Bcst 31 0 31 Note 2 Receive Bcst 32 Not Used 33 62 1 1 30...

Page 13: ...CK INVALID OVRWRT WCNT4 WCNT3 WCNT2 WCNT1 WCNT0 6 2 0 REMOTE TERMINAL MESSAGE LOG FORMAT Log Pointer Log Pointer Table Address Table 16Bit Subaddress Log Table Pointers 16Bit Receive Subaddress 1 Log...

Page 14: ...Command Word Message Time Word Data_Table_1_Adr 63 Max Data Control Word Time Tag Time Tag Data Words Status Data Table Receive Command Message Tag Message Control Transmit Command Message Time Word D...

Page 15: ...Command Message Tag Message Control Receive Command Message Time Word Transmit Command Data_Table_1_Adr 63 Max Data Control Word Time Tag Time Tag Transmit Status Data Words Data Table RT RT Command B...

Page 16: ...Command Message Time Word Data_Table_1_Adr 63 Max Data Control Word Time Tag Time Tag Status Data Word Data Table Transmit Mode Code Data Message Tag Message Control Receive Command Message Time Word...

Page 17: ...BLOCK STRUCTURE Block End Address Message Block Block Start Register Ram Message Block Message Block Last Word Address Register Tag Word Command Status Time Tag High Word Time Tag Low Word Data Words...

Page 18: ...BLOCK ORGANIZATION Block End Address Word Block Block Start Address Register Ram Word Block Last Word Address Register Word Monitor Structure Word Block Tag Word Command Status Data Time Tag High Wor...

Page 19: ...DDC Electronics K K Dai ichi Magami Bldg 8F 1 5 Koraku 1 chome Bunkyo ku Tokyo 112 0004 Japan Tel 81 3 3814 7688 Fax 81 3 3814 7689 Web site www ddcjapan co jp Asia Data Device Corporation RO Register...

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