H A R D W A R E O P E R A T I O N
Data Device Corporation
BU-65570/2i Manual
24
The BU-65572iX supports three types of response errors: no response,
a late response, or a response on the wrong bus. No response errors
may be programmed for a single bus (Bus A or Bus B) or for both buses.
Injecting a no response error on one bus provides a simple mechanism
for testing bus controller retry conditions. A late response may be
programmed in the range of 2 to 30
µ
secs in 1
µ
sec increments.
RT Intermessage Routines
The RT section of the BU-65572iX also supports intermessage routines.
Upon completion of a RT message the BU-65572iX's on-board
processor executes two intermessage routines. The data table that was
used by the RT for a given message specifies which intermessage
routines will be executed. Refer to TABLE 3 for a summary of the BU-
65572iX 's intermessage routines.
As with the Bus Controller operation, the RT intermessage routines
specify special actions to take place at the end of the current message
processing. One of the more common actions that are taken is to signal
the application that the hardware completed the message by generating
an interrupt to the system. Other actions will cause discretes to be set or
cleared and data tables to be swapped. And since each
RT / Sub-address can be assigned a block of data tables, each message
to the RT can result in different actions being taken.
BC/RT DATA TABLES
For each of the installed 1553 channels, the BU-65572iX maintains
1024 data tables within the shared RAM. Each data table may be up to
32 words in length. The total memory allocation for all data tables is
restricted to 12K words. These data tables are common to both BC and
RT. Internal lookup tables map each RT address, T/R, sub-address
combination (RT mode) and message number (BC mode) to a chosen
data table. Data tables may be read or written to in real time by the user
(‘ddcReadData’ or ‘ddcWriteData’) (see BU-69068 manual) and may be
either single or double buffered. Double buffering can be used to avoid
the memory access contention that occurs when the PC's application
and the 1553 bus access data tables simultaneously. The BU-65572iX
provides an optional block data mode in which the data table number
associated with a given RT message is incremented after completion of
the message. The block data mode is implemented as a circular data
structure. Each RT command (RT address, T/R, and sub-address) has
three data table numbers associated with it: first, last, and current. The
current data table number will be incremented after completion of
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