S/5 Anesthesia Monitor and S/5 Critical Care Monitor
Document No. 8002948
4
NAND
FLASH
4Mx8
80486
DX4/DX5
3.3V
MA,RAS,CAS
Buffer
CONTROL
PLD
IS
A
CO
NT
RO
L
S
D
[0
..1
5]
S
A
[0
..23]
A[2..31]
D[0..31]
CONTROL
SA[2..23]
SD[0..15]
ISA CONTROL
SA[0..1]
Buffer
BSA[0..23]
BSD[0.15]
BCONTROL
DUART
Buffer
TXDA..CTSC
232-Buffer
TXDD..RXD
D
ISA BUS
Audio
Generator
AUDIO
EEPROM
64Kx8
72 pin SIMM
DRAM
MODULE
16..32MB
PCMCIA
-controller
FLASH
CARD
BOOT
FLASH
2Mx16
5V->3.3V
REGULATOR
FREQUENCY
GENERATOR
14.318
MHz
XTAL
14.3MHz
7.3728MHz
XTAL
50MHz
3.3V
DAC
2 CH.
RADISYS
R400EX
PC-ChipSet
PS2
KEYB
CONN
5V
2 x serial cannel
SRAM
& RTC
8kx8
CP
U B
U
S
96-
pin c
onnec
to
r
Figure 2
CPU board block diagram, B-CPU5/B-CPU4
The CPU board, B-CPU5/B-CPU4 is made with PC-technology components. Radisys chipset and
PLD handle all timings and signaling for ISA type CPU bus.
The B-CPU5/B-CPU4 contains an onboard flash memory where software is downloaded from a
software card.
Powerfail or standby
When the monitor is turned to standby or the mains voltage fails, NMI-interrupt is generated by the
power control logic. The interrupt signal in the CPU means that all supply voltages 5V for
the CPU board will be switched off shortly. NMI interrupt service program then saves all necessary
parameters in the static RAM before supply voltages fail.
When hardware detects HALT command generated from power down; all the outputs to the CPU
motherboard are left floating in high impedance state. Only DRAM refreshing cycle continues to
occur. The halt state will continue until a RESET pulse from the power control logic circuit is
received.