USB3-FRM13_K Users Manual (Rev 1.0)
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- http://www.daqsystem.com
3.2 Functional Blocks
(1)
MDR-26 Connecter : J1, J2
Camera Link Base (J1), medium/Full (J2) Signal Connector
(2)
LVDS Link : U2, U3, U4
It is protected a circuit that the interface of high voltage higher than 3.3V CMOS Logic is
exchanged to normal 3.3V Logic Level.
(3)
FPGA : U6
All of the functions are controlled by the logic program of the FPGA.
(4)
Regulator : U14, U20, U21
The Regulator is for supplying the power (3.3V) to the board.
(5)
USB 3.0 Interface Chipset : U10
This block supports USB3.0 Super Speed interface.
(6)
DDR Memory : REF1, REF2
After save the data in a frame unit, transfer to PC through FPGA.
