DAQ system PCIe-AIO14, User Manual

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PCIe-AIO14 User Manual (Rev 1.2)
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http://www.daqsystem.com
[Fig 5-3. Trigger Mode Data]
5.4.6 Sampling Timing
Timing of acquisition and execution according to the set sampling rate is shown in the following
figure. If more than one channel is selected, the time interval to the adjacent channel is the ADC
highest sampling rate 2Msps and the interval between channel blocks maintains the time of the
set sampling rate.
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- CH 0, 3 ( ), 100Ksps
1/2Msps = 500nsec 1/100Ksps = 10usec
[Fig 5-4. Sampling Timong]